// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//   
// File name    : CLASS_8ME_TOP
// Module name  : CLASS_8ME_TOP
// Full name    :  
// Time         : 2021 
// Author       : Haoxiaofei 
// Email        : 1531804419@qq.com
// Data         : 
// Version      : V 2.4
// 
// Abstract     :
// Edited by    : Wangzekun
// 
// Modification history
// -----------------------------------------------------------------
// v2.1 
// v2.2 zhangjianyuan
// v2.3 line 416/425
// v2.4 fieldn_valid signals
//
// **********************************************************************************************************************
// CPU\u5168\u914d\u7f6e\u63a5\u53e3  \u5728\u4e0b\u90e8\u6ce8\u91ca\u6389\u4e86  \u76ee\u524d\u4f7f\u7528\u7684\u662f\u672a\u540c\u6b65\u8f6c\u53d1\u8868\u914d\u7f6e\u63a5\u53e3\u7684  \u4ee5\u4fbf\u76ee\u524d\u4eff\u771f\uff0c\u4e0a\u677f
//
// **********************************************************************************************************************
//DEFINE MODULE PORT
//*******************

`include "top_define.v"
module CLASS_8ME_TOP(
    input wire rst_n,
    input wire clk,
    input wire [11:0]ram_dp_cfg_register,
    input wire [9:0] ram_2p_cfg_register,

    //CPU\u548c8ME\u63a5\u53e3
    `ifndef NO_CPU_MODE 
      //CPU\u548c8ME\u63a5\u53e3
      input  wire [31:0]                np_cpu_wr_data              ,
      input  wire [16:0]                np_cpu_addr                 ,
      input  wire [ 1:0]                np_cpu_ram_ctr              ,
      output reg  [31:0]                np_cpu_rd_data              ,
      output reg                        class_8me_rd_vld            ,
    `else
      input  wire [31:0]                np_cpu_wr_data              ,
      input  wire [16:0]                np_cpu_addr                 ,
      input  wire [ 1:0]                np_cpu_ram_ctr              ,
      output reg  [31:0]                np_cpu_rd_data              ,
   `endif

    input  wire [0:1023]pktheader_vector,
    input  wire vector_rdy,

    output reg [88:0]action_pkt_o,//\u5305\u64cd\u4f5c\u6307\u4ee4\u7801
    output reg action_pkt_en_o,
    output reg me1_action_en_o_ff,

//ME7 \u914d\u7f6e\u5355\u64ad\u8f6c\u53d1\u8868
      output wire [9:0]   bus1_table_addr2            ,
      output wire [9:0]   bus1_table_ram_addr_convert ,
      output wire [71:0]  bus1_table_data2            ,
      output wire [71:0]  bus1_table_ram_data_convert ,
      output wire         bus1_table_wren2            ,
      output wire         bus1_table_ram_wr_en_convert,
      input  wire [9:0]   bus2_table_addr2            ,
      input  wire [9:0]   bus2_table_ram_addr_convert ,
      input  wire [71:0]  bus2_table_data2            ,
      input  wire [71:0]  bus2_table_ram_data_convert ,
      input  wire         bus2_table_wren2            ,
      input  wire         bus2_table_ram_wr_en_convert,
      input  wire [9:0]   bus3_table_addr2            ,
      input  wire [9:0]   bus3_table_ram_addr_convert ,
      input  wire [71:0]  bus3_table_data2            ,
      input  wire [71:0]  bus3_table_ram_data_convert ,
      input  wire         bus3_table_wren2            ,
      input  wire         bus3_table_ram_wr_en_convert,
      input  wire [9:0]   bus4_table_addr2            ,
      input  wire [9:0]   bus4_table_ram_addr_convert ,
      input  wire [71:0]  bus4_table_data2            ,
      input  wire [71:0]  bus4_table_ram_data_convert ,
      input  wire         bus4_table_wren2            ,
      input  wire         bus4_table_ram_wr_en_convert,
    `ifdef NO_CPU_MODE
    input  wire         himac_loopback_on_off,
    input  wire         collision_detect_on_off,
    output wire [31:0]  collision_port_1,
    output wire [31:0]  collision_port_2,
    output wire [31:0]  collision_mac_addr_1,
    output wire [31:0]  collision_mac_addr_2,
    output wire         collision_wren,
    input  wire         broadcast_pkt_pass,
    output wire         broadcast_pkt_ack,
    input  wire         unknow_pkt_pass,
    output wire         unknow_pkt_ack,
    `endif
    //with uni_cam_module
    output wire         unicam_busy,
    `ifdef NO_CPU_MODE
    input  wire         CPU_unicam_wren,
    input  wire [11:0]  CPU_unicam_addr,
    input  wire [31:0]  CPU_unicam_din ,
    output wire [31:0]  CPU_unicam_dout,
    input  wire         CPU_unicam_live_val ,
    input  wire [31:0]  CPU_unicam_live_time,
    `endif

      output wire         unicam_init_done,
    //with receive_sch
    input  wire [47:0]  mac_sour  ,
    input  wire [47:0]  mac_dest  ,
      input  wire         uni_addr_en,
    input  wire [ 3:0]  port_sour ,
    output wire [ 3:0]  uni_outport   ,
    output wire         uni_outport_en,
    output wire         uni_lookup_fail , 
  //ME8 \u914d\u7f6e\u7ec4\u64ad\u8f6c\u53d1\u8868
  `ifdef NO_CPU_MODE
      input  wire         CPU_mulcam_wren,
      input  wire [ 31:0] CPU_mulcam_modify,
      input  wire [ 31:0] CPU_mulcam_group_mac,
      input  wire [ 31:0] CPU_mulcam_member,
      input  wire         CPU_mulcam_rden,
      input  wire [ 11:0] CPU_mulcam_addr,
      output wire [ 31:0] CPU_mulcam_dout,
  `endif
           //\u63a5\u6536\u8c03\u5ea6--\u7ec4\u64ad\u8f6c\u53d1\u8868
    output wire         multi_busy      ,
    input  wire         multi_addr_en   ,
    output wire [  7:0] multi_outport   ,
    output wire         multi_outport_en,   
           //\u521d\u59cb\u5316\u5b8c\u6210
    output wire         multicam_init_done,
    output reg  [  1:0] pkt_mod_ctl      //5.23, xym
    ); 

//*******************
//DEFINE LOCAL PARAMETER
//*******************
//parameter(s)

//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS
reg[3:0]schduler;
reg[84:0]me1_action_o_ff;
reg[3:0]me3_4_action_o_ff;
reg[3:0]me5_action_o_ff;
reg[3:0]me6_action_o_ff;
// reg me1_action_en_o_ff;
reg field0_valid;
reg field1_valid;
reg field2_valid;
reg field3_valid;
reg field4_valid;
reg field5_valid;

//WIRES
wire [84:0]me1_action_o;   
wire       me1_action_en_o;

wire [3:0] me2_action_o;   
//wire       me2_action_en_o;

wire [3:0] me3_4_action_o;   
//wire       me3_4_action_en_o;

wire [3:0] me5_action_o;   
//wire       me5_action_en_o;

wire [3:0] me6_action_o;   
//wire       me6_action_en_o;

wire [31:0]match_res_t3;
wire lookup_done4;

//ME1
reg [31:0]ctr_field0_0;
reg [31:0]ctr_field0_1;
reg [31:0]ctr_field0_2;
reg [31:0]ctr_field0_3;
reg [31:0]ctr_field0_4;
reg [31:0]ctr_field0_5;
reg [31:0]ctr_field0_6;
reg [31:0]ctr_field0_7;
//ME2
reg [31:0]ctr_field1_0;
reg [31:0]ctr_field1_1;
reg [31:0]ctr_field1_2;
reg [31:0]ctr_field1_3;
//ME3
reg [31:0]ctr_field2_0;
reg [31:0]ctr_field2_1;
reg [31:0]ctr_field2_2;
reg [31:0]ctr_field2_3;
reg [31:0]ctr_field2_4;
reg [31:0]ctr_field2_5;
reg [31:0]ctr_field2_6;
reg [31:0]ctr_field2_7;
//ME4
reg [31:0]ctr_field3_0;
reg [31:0]ctr_field3_1;
reg [31:0]ctr_field3_2;
reg [31:0]ctr_field3_3;
reg [31:0]ctr_field3_4;
reg [31:0]ctr_field3_5;
reg [31:0]ctr_field3_6;
reg [31:0]ctr_field3_7;
//ME5
reg [31:0]ctr_field4_0;
reg [31:0]ctr_field4_1;
reg [31:0]ctr_field4_2;
reg [31:0]ctr_field4_3;
reg [31:0]ctr_field4_4;
reg [31:0]ctr_field4_5;
reg [31:0]ctr_field4_6;
reg [31:0]ctr_field4_7;
//ME6
reg [31:0]ctr_field5_0;
reg [31:0]ctr_field5_1;
reg [31:0]ctr_field5_2;
reg [31:0]ctr_field5_3;
reg [31:0]ctr_field5_4;
reg [31:0]ctr_field5_5;
reg [31:0]ctr_field5_6;
reg [31:0]ctr_field5_7;

wire [255:0]ctr_field_me1;
wire [127:0]ctr_field_me2;
wire [255:0]ctr_field_me3;
wire [255:0]ctr_field_me4;
wire [255:0]ctr_field_me5;
wire [255:0]ctr_field_me6;

// wire [15:0]  me_array_bv1_dpram_addr       ;
reg          me_array_bv1_dpram_wen        ;
// wire [31:0]  me_array_bv1_dpram_wdata      ;
reg          me_array_bv1_dpram_ren        ;
wire [31:0]  me_array_bv1_dpram_rdata      ;
// wire [15:0]  me_array_hash2_dpram_addr     ;
reg          me_array_hash2_dpram_wen      ;
// wire [31:0]  me_array_hash2_dpram_wdata    ;
// wire [15:0]  me_array_rbve1_3_dpram_addr   ;
reg          me_array_rbve1_3_dpram_wen    ;
// wire [31:0]  me_array_rbve1_3_dpram_wdata  ;
reg          me_array_rbve1_3_dpram_ren    ;
wire [31:0]  me_array_rbve1_3_dpram_rdata  ;
// wire [15:0]  me_array_rbve2_3_dpram_addr   ;
reg          me_array_rbve2_3_dpram_wen    ;
// wire [31:0]  me_array_rbve2_3_dpram_wdata  ;
reg          me_array_rbve2_3_dpram_ren    ;
wire [31:0]  me_array_rbve2_3_dpram_rdata  ;
// wire [15:0]  me_array_bv4_dpram_addr       ;
reg          me_array_bv4_dpram_wen        ;
// wire [31:0]  me_array_bv4_dpram_wdata      ;
reg          me_array_bv4_dpram_ren        ;
wire [31:0]  me_array_bv4_dpram_rdata      ;
// wire [15:0]  me_array_bv5_dpram_addr       ;
reg          me_array_bv5_dpram_wen        ;
// wire [31:0]  me_array_bv5_dpram_wdata      ;
reg          me_array_bv5_dpram_ren        ;
wire [31:0]  me_array_bv5_dpram_rdata      ;
// wire [15:0]  me_array_bv6_dpram_addr       ;
reg          me_array_bv6_dpram_wen        ;
// wire [31:0]  me_array_bv6_dpram_wdata      ;
reg          me_array_bv6_dpram_ren        ;
wire [31:0]  me_array_bv6_dpram_rdata      ;
// wire [15:0]  me_array_action1_dpram_addr   ;
reg          me_array_action1_dpram_wen    ;
// wire [31:0]  me_array_action1_dpram_wdata  ;
reg          me_array_action1_dpram_ren    ;
wire [31:0]  me_array_action1_dpram_rdata  ;
// wire [15:0]  me_array_action4_dpram_addr   ;
reg          me_array_action4_dpram_wen    ;
// wire [31:0]  me_array_action4_dpram_wdata  ;
reg          me_array_action4_dpram_ren    ;
wire [31:0]  me_array_action4_dpram_rdata  ;
// wire [15:0]  me_array_action5_dpram_addr   ;
reg          me_array_action5_dpram_wen    ;
// wire [31:0]  me_array_action5_dpram_wdata  ;
reg          me_array_action5_dpram_ren    ;
wire [31:0]  me_array_action5_dpram_rdata  ;
// wire [15:0]  me_array_action6_dpram_addr   ;
reg          me_array_action6_dpram_wen    ;
// wire [31:0]  me_array_action6_dpram_wdata  ;
reg          me_array_action6_dpram_ren    ;
wire [31:0]  me_array_action6_dpram_rdata  ;

reg  [31:0]  me_array_filed0_dpram_rdata   ;
reg  [31:0]  me_array_filed1_dpram_rdata   ;
reg  [31:0]  me_array_filed2_dpram_rdata   ;
reg  [31:0]  me_array_filed3_dpram_rdata   ;
reg  [31:0]  me_array_filed4_dpram_rdata   ;
reg  [31:0]  me_array_filed5_dpram_rdata   ;

wire rd_field;
// wire rd_field1;
// wire rd_field2;
// wire rd_field3;
// wire rd_field4;
// wire rd_field5;
// wire rd_field6;

wire me_array_bv1_dpram_valid     ;
wire me_array_rbve1_3_dpram_valid ;
wire me_array_rbve2_3_dpram_valid ;
wire me_array_bv4_dpram_valid     ;
wire me_array_bv5_dpram_valid     ;
wire me_array_bv6_dpram_valid     ;
wire me_array_action1_dpram_valid ;
wire me_array_action4_dpram_valid ;
wire me_array_action5_dpram_valid ;
wire me_array_action6_dpram_valid ;

wire [5:0]  field_rd_sel     ;
wire [5:0]  match_rd_sel     ;
wire [3:0]  action_rd_sel    ;
wire [2:0]  rd_data_sel      ;
reg [31:0]  field_rd_data    ;
reg [31:0]  match_rd_data    ;
reg [31:0]  action_rd_data   ;

reg [31:0] np_cpu_rd_data_temp;
wire [31:0] class_rd_data;

reg class_rd_en_tmp;
wire class_rd_en;
reg [31:0] uni_mul_rd_data;
reg [31:0] reg_rd_data;
reg uni_mul_rd_en;

`ifndef NO_CPU_MODE
// reg       CPU_unicam_wren_ff;
// reg [11:0]CPU_unicam_addr_ff;    
// reg [31:0]CPU_unicam_din_ff;

reg       CPU_mulcam_wren_ff;

wire [31:0]  CPU_unicam_dout;
wire [ 31:0] CPU_mulcam_dout;
wire [3:0]  collision_port_1;
wire [3:0]  collision_port_2;
wire [31:0]  collision_mac_addr_1;
wire [15:0]  collision_mac_addr_2;
wire         collision_wren;
wire         broadcast_pkt_ack;
wire         unkonw_pkt_ack;

reg         CPU_unicam_wren;
reg         CPU_unicam_rden;
wire        CPU_mulcam_wren;
wire        CPU_mulcam_rden;
reg         CPU_reg_wren;
reg         CPU_reg_rden;
wire        CPU_unicam_vld;
wire        CPU_mulcam_vld;

wire [11:0]  CPU_unicam_addr;
wire [31:0]  CPU_unicam_din ;
reg   CPU_unicam_live_val ;
reg [31:0]  CPU_unicam_live_time;

reg [ 31:0] CPU_mulcam_modify;
reg [ 31:0] CPU_mulcam_group_mac;
reg [ 31:0] CPU_mulcam_member;
wire [ 11:0] CPU_mulcam_addr;
reg      himac_loopback_on_off;
reg    collision_detect_on_off;
reg    broadcast_pkt_pass;
reg    unknow_pkt_pass;
wire [4:0]me2_hash_error;
`endif    


reg         CPU_reg_rden_d1   ;
reg         uni_mul_rd_vld    ;
reg         CPU_reg_rd_vld    ;


reg field_rd_en;
reg match_rd_en;
reg action_rd_en;
//*********************
//INSTANTCE MODULE
//*********************
//=============================================================
reg [16:0]  np_cpu_addr_d1    ;// 2022.5.9 xym
// reg [15:0]  np_cpu_addr_d1    ;
reg [31:0]  np_cpu_wdata_d1;
//=============================================================
//ME1
ME1 U_ME1(
    .clk(clk),
    .rst_n(rst_n),
    .vector_rdy(vector_rdy),
    .ctr_field(ctr_field_me1),//216'h200000007_100000100_200000005_400000104_200000004_400000204
    .pktheader_vector(pktheader_vector),

    .ram_addr                      ( { ~np_cpu_addr_d1[10],  np_cpu_addr_d1[9:0] } ),// me1 2+3+6=11, 2022.5.9 xym
    .ram_data                      (np_cpu_wdata_d1 ),
    .cpu_wen                       (me_array_bv1_dpram_wen   ),
    .cpu_ren                       (me_array_bv1_dpram_ren   ),
    .me_array_bv1_dpram_valid      (me_array_bv1_dpram_valid ),
    .read_data_cpu                 (me_array_bv1_dpram_rdata ),

    .me_array_action1_dpram_addr   ( np_cpu_addr_d1[6:0] ),// act1 2+5=7, 2022.5.9 xym
    .me_array_action1_dpram_wen    (me_array_action1_dpram_wen   ),
    .me_array_action1_dpram_wdata  (np_cpu_wdata_d1 ),
    .me_array_action1_dpram_ren    (me_array_action1_dpram_ren   ),
    .me_array_action1_dpram_valid  (me_array_action1_dpram_valid ),
    .me_array_action1_dpram_rdata  (me_array_action1_dpram_rdata ),

    .act_pkt_process(me1_action_o   ),
    .action_en_o    (me1_action_en_o)
    );

//=======================================================================
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_bv1_dpram_wen <= 1'b0;
    else if(np_cpu_ram_ctr[1] && (np_cpu_addr[16:10]>=`BV1_BASE_ADDR) && (np_cpu_addr[16:10]<`ACTION1_BASE_ADDR))
        me_array_bv1_dpram_wen <= 1'b1;
    else
        me_array_bv1_dpram_wen <= 1'b0;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_bv1_dpram_ren <= 1'b0;
    else if(np_cpu_ram_ctr[0] && (np_cpu_addr[16:10]>=`BV1_BASE_ADDR) && (np_cpu_addr[16:10]<`ACTION1_BASE_ADDR))
        me_array_bv1_dpram_ren <= 1'b1;
    else
        me_array_bv1_dpram_ren <= 1'b0;
end
//----------------------------------------------------------------
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_action1_dpram_wen <= 1'b0;
    else if(np_cpu_ram_ctr[1] && np_cpu_addr[16:10]>=`ACTION1_BASE_ADDR && np_cpu_addr[16:10]<`HASH2_BASE_ADDR)
        me_array_action1_dpram_wen <= 1'b1;
    else
        me_array_action1_dpram_wen <= 1'b0;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_action1_dpram_ren <= 1'b0;
    else if(np_cpu_ram_ctr[0] && np_cpu_addr[16:10]>=`ACTION1_BASE_ADDR && np_cpu_addr[16:10]<`HASH2_BASE_ADDR)
        me_array_action1_dpram_ren <= 1'b1;
    else
        me_array_action1_dpram_ren <= 1'b0;
end
//=======================================================================
// assign me_array_bv1_dpram_addr      = np_cpu_addr ;    
// assign me_array_bv1_dpram_wdata     = np_cpu_wr_data    ;
// assign me_array_bv1_dpram_wen       = np_cpu_ram_ctr[27]; 
// assign me_array_bv1_dpram_ren       = np_cpu_ram_ctr[26];
// assign me_array_action1_dpram_addr  = np_cpu_addr ;
// assign me_array_action1_dpram_wen   = np_cpu_ram_ctr[9];
// assign me_array_action1_dpram_wdata = np_cpu_wr_data    ;
// assign me_array_action1_dpram_ren   = np_cpu_ram_ctr[8];
//ME2
ME2 U_ME2(
    .clk(clk),
    .rst_n(rst_n),
    .vector_rdy(vector_rdy),
    .ctr_field(ctr_field_me2),//216'h200000007_100000100_200000005_400000104_200000004_400000204
    .pktheader_vector(pktheader_vector),

    // .ram_addr(me_array_hash2_dpram_addr ),
    .ram_data(np_cpu_wdata_d1),
    .cpu_wen (me_array_hash2_dpram_wen  ),
    // .cpu_ren(me_array_hash2_dpram_ren),
    // .read_data_cpu(me_array_hash2_dpram_rdata),

    .schduler_ren       (me1_action_en_o),
    .schduler_i_o       (me2_action_o),
    .action_en_o        (),
    .error              (me2_hash_error)
    );
// assign me_array_hash2_dpram_addr  = np_cpu_addr       ;
// assign me_array_hash2_dpram_wdata = np_cpu_wr_data    ;
//============================================================
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_hash2_dpram_wen <= 1'b0;
    else if(np_cpu_ram_ctr[1] && np_cpu_addr[16:10]>=`HASH2_BASE_ADDR && np_cpu_addr[16:10]<`RBVE31_BASE_ADDR)
        me_array_hash2_dpram_wen <= 1'b1;
    else
        me_array_hash2_dpram_wen <= 1'b0;
end
// assign me_array_hash2_dpram_wen   = np_cpu_ram_ctr[25];
//=============================================================
//ME3
ME3 U_ME3(
    .clk(clk),
    .rst_n(rst_n),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .vector_rdy(vector_rdy),
    .ctr_field(ctr_field_me3),//216'h200000007_100000100_200000005_400000104_200000004_400000204
    .pktheader_vector(pktheader_vector),

    .ram_addr1                      ( { ~np_cpu_addr_d1[14], np_cpu_addr_d1[13:0]} ),// rbve1 4+2+8=14, 1 for sel, 2022.5.9 xym
    .ram_data1                      (np_cpu_wdata_d1   ),
    .cpu_wen1                       (me_array_rbve1_3_dpram_wen     ),
    .cpu_ren1                       (me_array_rbve1_3_dpram_ren     ),
    .read_data_cpu1                 (me_array_rbve1_3_dpram_rdata   ),
    .read_data_valid1               (me_array_rbve1_3_dpram_valid   ),

    .ram_addr2                      ( { ~np_cpu_addr_d1[14], np_cpu_addr_d1[13:0] } ),// rbve2 4+2(1)+8=14, 1 for sel, 2022.5.9 xym
    .cpu_wen2                       (me_array_rbve2_3_dpram_wen     ),
    .ram_data2                      (np_cpu_wdata_d1   ),
    .cpu_ren2                       (me_array_rbve2_3_dpram_ren     ),
    .read_data_cpu2                 (me_array_rbve2_3_dpram_rdata   ),
    .read_data_valid2               (me_array_rbve2_3_dpram_valid   ),
   
    .match_res_t3(match_res_t3),//out
    .lookup_done4(lookup_done4)//in \u7528\u4e8e\u65f6\u5e8f\u540c\u6b65
    );
//=======================================================================
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_rbve1_3_dpram_wen <= 1'b0;
    else if(np_cpu_ram_ctr[1] && np_cpu_addr[16:10]>=`RBVE31_BASE_ADDR_L && np_cpu_addr[16:10]<`RBVE32_BASE_ADDR_L)
        me_array_rbve1_3_dpram_wen <= 1'b1;
    else
        me_array_rbve1_3_dpram_wen <= 1'b0;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_rbve1_3_dpram_ren <= 1'b0;
    else if(np_cpu_ram_ctr[0] && np_cpu_addr[16:10]>=`RBVE31_BASE_ADDR_L && np_cpu_addr[16:10]<`RBVE32_BASE_ADDR_L)
        me_array_rbve1_3_dpram_ren <= 1'b1;
    else
        me_array_rbve1_3_dpram_ren <= 1'b0;
end
//----------------------------------------------------------------
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_rbve2_3_dpram_wen <= 1'b0;
    else if(np_cpu_ram_ctr[1] && np_cpu_addr[16:10]>=`RBVE32_BASE_ADDR_L && np_cpu_addr[16:10]<`RBVE32_BASE_ADDR_H)
        me_array_rbve2_3_dpram_wen <= 1'b1;
    else
        me_array_rbve2_3_dpram_wen <= 1'b0;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_rbve2_3_dpram_ren <= 1'b0;
    else if(np_cpu_ram_ctr[0] && np_cpu_addr[16:10]>=`RBVE32_BASE_ADDR_L && np_cpu_addr[16:10]<`RBVE32_BASE_ADDR_H)
        me_array_rbve2_3_dpram_ren <= 1'b1;
    else
        me_array_rbve2_3_dpram_ren <= 1'b0;
end
//=======================================================================
// assign me_array_rbve1_3_dpram_addr  = np_cpu_addr ; 
// assign me_array_rbve1_3_dpram_wdata = np_cpu_wr_data    ;
// assign me_array_rbve1_3_dpram_wen   = np_cpu_ram_ctr[23];
// assign me_array_rbve1_3_dpram_ren   = np_cpu_ram_ctr[22];
// assign me_array_rbve2_3_dpram_addr  = np_cpu_addr ;
// assign me_array_rbve2_3_dpram_wen   = np_cpu_ram_ctr[21];
// assign me_array_rbve2_3_dpram_wdata = np_cpu_wr_data    ;
// assign me_array_rbve2_3_dpram_ren   = np_cpu_ram_ctr[20];
//ME4
ME4 U_ME4(
     .clk(clk),
    .rst_n(rst_n),
    .vector_rdy(vector_rdy),
    .ctr_field(ctr_field_me4),//216'h200000007_100000100_200000005_400000104_200000004_400000204
    .pktheader_vector(pktheader_vector),

    .ram_addr                       ( np_cpu_addr_d1[10:0] ),// me4 2+3+6=11, 2022.5.9 xym
    .ram_data                       (np_cpu_wdata_d1      ),
    .cpu_wen                        (me_array_bv4_dpram_wen         ),
    .cpu_ren                        (me_array_bv4_dpram_ren         ),
    .read_data_cpu                  (me_array_bv4_dpram_rdata       ),
    .me_array_bv4_dpram_valid       (me_array_bv4_dpram_valid       ),

    .me_array_action4_dpram_addr    ( np_cpu_addr_d1[4:0] ),// act4 5, 2022.5.9 xym
    .me_array_action4_dpram_wen     (me_array_action4_dpram_wen     ),
    .me_array_action4_dpram_wdata   (np_cpu_wdata_d1   ),
    .me_array_action4_dpram_ren     (me_array_action4_dpram_ren     ),
    .me_array_action4_dpram_rdata   (me_array_action4_dpram_rdata   ),
    .me_array_action4_dpram_valid   (me_array_action4_dpram_valid   ),

    .lookup_done4(lookup_done4),//out
    .match_res_t3(match_res_t3),//in 
    .action_o(me3_4_action_o),
    .action_en_o()
    );

//=======================================================================
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_bv4_dpram_wen <= 1'b0;
    else if(np_cpu_ram_ctr[1] && np_cpu_addr[16:10]>=`BV4_BASE_ADDR && np_cpu_addr[16:10]<`ACTION4_BASE_ADDR)
        me_array_bv4_dpram_wen <= 1'b1;
    else
        me_array_bv4_dpram_wen <= 1'b0;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_bv4_dpram_ren <= 1'b0;
    else if(np_cpu_ram_ctr[0] && np_cpu_addr[16:10]>=`BV4_BASE_ADDR && np_cpu_addr[16:10]<`ACTION4_BASE_ADDR)
        me_array_bv4_dpram_ren <= 1'b1;
    else
        me_array_bv4_dpram_ren <= 1'b0;
end
//----------------------------------------------------------------
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_action4_dpram_wen <= 1'b0;
    else if(np_cpu_ram_ctr[1] && np_cpu_addr[16:10]>=`ACTION4_BASE_ADDR && np_cpu_addr[16:10]<`BV5_BASE_ADDR)
        me_array_action4_dpram_wen <= 1'b1;
    else
        me_array_action4_dpram_wen <= 1'b0;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_action4_dpram_ren <= 1'b0;
    else if(np_cpu_ram_ctr[0] && np_cpu_addr[16:10]>=`ACTION4_BASE_ADDR && np_cpu_addr[16:10]<`BV5_BASE_ADDR)
        me_array_action4_dpram_ren <= 1'b1;
    else
        me_array_action4_dpram_ren <= 1'b0;
end
//=======================================================================
// assign me_array_bv4_dpram_addr      = np_cpu_addr ;
// assign me_array_bv4_dpram_wdata     = np_cpu_wr_data    ;
// assign me_array_bv4_dpram_wen       = np_cpu_ram_ctr[19];
// assign me_array_bv4_dpram_ren       = np_cpu_ram_ctr[18];
// assign me_array_action4_dpram_addr  = np_cpu_addr ;
// assign me_array_action4_dpram_wen   = np_cpu_ram_ctr[7];
// assign me_array_action4_dpram_wdata = np_cpu_wr_data    ;
// assign me_array_action4_dpram_ren   = np_cpu_ram_ctr[6];
//ME5
ME5 U_ME5(
     .clk(clk),
    .rst_n(rst_n),
    .vector_rdy(vector_rdy),
    .ctr_field(ctr_field_me5),//216'h200000007_100000100_200000005_400000104_200000004_400000204
    .pktheader_vector(pktheader_vector),

    .ram_addr                       ( { ~np_cpu_addr_d1[10],  np_cpu_addr_d1[9:0] } ),// me5 2+3+6=11, 2022.5.9 xym
    .ram_data                       (np_cpu_wdata_d1       ),
    .cpu_wen                        (me_array_bv5_dpram_wen         ),
    .cpu_ren                        (me_array_bv5_dpram_ren         ),
    .read_data_cpu                  (me_array_bv5_dpram_rdata       ),
    .me_array_bv5_dpram_valid       (me_array_bv5_dpram_valid       ),

    .me_array_action5_dpram_addr    ( np_cpu_addr_d1[4:0] ),// act5 5, 2022.5.9 xym
    .me_array_action5_dpram_wen     (me_array_action5_dpram_wen     ),
    .me_array_action5_dpram_wdata   (np_cpu_wdata_d1   ),
    .me_array_action5_dpram_ren     (me_array_action5_dpram_ren     ),
    .me_array_action5_dpram_rdata   (me_array_action5_dpram_rdata   ),
    .me_array_action5_dpram_valid   (me_array_action5_dpram_valid   ),

    .action_o(me5_action_o),
    .action_en_o()
    );

//=======================================================================
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_bv5_dpram_wen <= 1'b0;
    else if(np_cpu_ram_ctr[1] && np_cpu_addr[16:10]>=`BV5_BASE_ADDR && np_cpu_addr[16:10]<`ACTION5_BASE_ADDR)
        me_array_bv5_dpram_wen <= 1'b1;
    else
        me_array_bv5_dpram_wen <= 1'b0;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_bv5_dpram_ren <= 1'b0;
    else if(np_cpu_ram_ctr[0] && np_cpu_addr[16:10]>=`BV5_BASE_ADDR && np_cpu_addr[16:10]<`ACTION5_BASE_ADDR)
        me_array_bv5_dpram_ren <= 1'b1;
    else
        me_array_bv5_dpram_ren <= 1'b0;
end
//----------------------------------------------------------------
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_action5_dpram_wen <= 1'b0;
    else if(np_cpu_ram_ctr[1] && np_cpu_addr[16:10]>=`ACTION5_BASE_ADDR && np_cpu_addr[16:10]<`BV6_BASE_ADDR)
        me_array_action5_dpram_wen <= 1'b1;
    else
        me_array_action5_dpram_wen <= 1'b0;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_action5_dpram_ren <= 1'b0;
    else if(np_cpu_ram_ctr[0] && np_cpu_addr[16:10]>=`ACTION5_BASE_ADDR && np_cpu_addr[16:10]<`BV6_BASE_ADDR)
        me_array_action5_dpram_ren <= 1'b1;
    else
        me_array_action5_dpram_ren <= 1'b0;
end
//==================================================================
// assign me_array_bv5_dpram_addr       = np_cpu_addr ; 
// assign me_array_bv5_dpram_wdata      = np_cpu_wr_data    ; 
// assign me_array_bv5_dpram_wen        = np_cpu_ram_ctr[17]; 
// assign me_array_bv5_dpram_ren        = np_cpu_ram_ctr[16]; 
// assign me_array_action5_dpram_addr   = np_cpu_addr ; 
// assign me_array_action5_dpram_wen    = np_cpu_ram_ctr[5]; 
// assign me_array_action5_dpram_wdata  = np_cpu_wr_data    ; 
// assign me_array_action5_dpram_ren    = np_cpu_ram_ctr[4];
//ME6
ME6 U_ME6(
     .clk(clk),
    .rst_n(rst_n),
    .vector_rdy(vector_rdy),
    .ctr_field(ctr_field_me6),//216'h200000007_100000100_200000005_400000104_200000004_400000204
    .pktheader_vector(pktheader_vector),

    .ram_addr                       ( np_cpu_addr_d1[10:0] ),// me6 2+3+6=11, 2022.5.9 xym
    .ram_data                       (np_cpu_wdata_d1      ),
    .cpu_wen                        (me_array_bv6_dpram_wen         ),
    .cpu_ren                        (me_array_bv6_dpram_ren         ),
    .read_data_cpu                  (me_array_bv6_dpram_rdata       ),
    .me_array_bv6_dpram_valid       (me_array_bv6_dpram_valid       ),

    .me_array_action6_dpram_addr    ( np_cpu_addr_d1[4:0] ),// act6 5, 2022.5.9 xym
    .me_array_action6_dpram_wen     (me_array_action6_dpram_wen     ),
    .me_array_action6_dpram_wdata   (np_cpu_wdata_d1   ),
    .me_array_action6_dpram_ren     (me_array_action6_dpram_ren     ),
    .me_array_action6_dpram_rdata   (me_array_action6_dpram_rdata   ),
    .me_array_action6_dpram_valid   (me_array_action6_dpram_valid   ),

    .action_o(me6_action_o),
    .action_en_o()
    );

//=======================================================================
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_bv6_dpram_wen <= 1'b0;
    else if(np_cpu_ram_ctr[1] && np_cpu_addr[16:10]>=`BV6_BASE_ADDR && np_cpu_addr[16:10]<`ACTION6_BASE_ADDR)
        me_array_bv6_dpram_wen <= 1'b1;
    else
        me_array_bv6_dpram_wen <= 1'b0;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_bv6_dpram_ren <= 1'b0;
    else if(np_cpu_ram_ctr[0] && np_cpu_addr[16:10]>=`BV6_BASE_ADDR && np_cpu_addr[16:10]<`ACTION6_BASE_ADDR)
        me_array_bv6_dpram_ren <= 1'b1;
    else
        me_array_bv6_dpram_ren <= 1'b0;
end
//----------------------------------------------------------------
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_action6_dpram_wen <= 1'b0;
    else if(np_cpu_ram_ctr[1] && np_cpu_addr[16:10]>=`ACTION6_BASE_ADDR && np_cpu_addr[16:10]<`ME7_BASE_ADDR)
        me_array_action6_dpram_wen <= 1'b1;
    else
        me_array_action6_dpram_wen <= 1'b0;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        me_array_action6_dpram_ren <= 1'b0;
    else if(np_cpu_ram_ctr[0] && np_cpu_addr[16:10]>=`ACTION6_BASE_ADDR && np_cpu_addr[16:10]<`ME7_BASE_ADDR)
        me_array_action6_dpram_ren <= 1'b1;
    else
        me_array_action6_dpram_ren <= 1'b0;
end
//==================================================================
// assign me_array_bv6_dpram_addr       = np_cpu_addr ; 
// assign me_array_bv6_dpram_wdata      = np_cpu_wr_data    ; 
// assign me_array_bv6_dpram_wen        = np_cpu_ram_ctr[15]; 
// assign me_array_bv6_dpram_ren        = np_cpu_ram_ctr[14]; 
// assign me_array_action6_dpram_addr   = np_cpu_addr ; 
// assign me_array_action6_dpram_wen    = np_cpu_ram_ctr[3]; 
// assign me_array_action6_dpram_wdata  = np_cpu_wr_data    ; 
// assign me_array_action6_dpram_ren    = np_cpu_ram_ctr[2]; 
//ME7\u5355\u64ad\u8f6c\u53d1\u8868
    cam_top U_ME7
        (
            .clk                     (clk),
            .rst_n                   (rst_n),
            .ram_dp_cfg_register     (ram_dp_cfg_register),
            .ram_2p_cfg_register     (ram_2p_cfg_register),
            //\u56db\u603b\u7ebf\u540c\u6b65\u63a5\u53e3
            .bus1_table_addr2            (bus1_table_addr2            ),
            .bus1_table_ram_addr_convert (bus1_table_ram_addr_convert ),
            .bus1_table_data2            (bus1_table_data2            ),
            .bus1_table_ram_data_convert (bus1_table_ram_data_convert ),
            .bus1_table_wren2            (bus1_table_wren2            ),
            .bus1_table_ram_wr_en_convert(bus1_table_ram_wr_en_convert),
            .bus2_table_addr2            (bus2_table_addr2            ),
            .bus2_table_ram_addr_convert (bus2_table_ram_addr_convert ),
            .bus2_table_data2            (bus2_table_data2            ),
            .bus2_table_ram_data_convert (bus2_table_ram_data_convert ),
            .bus2_table_wren2            (bus2_table_wren2            ),
            .bus2_table_ram_wr_en_convert(bus2_table_ram_wr_en_convert),
            .bus3_table_addr2            (bus3_table_addr2            ),
            .bus3_table_ram_addr_convert (bus3_table_ram_addr_convert ),
            .bus3_table_data2            (bus3_table_data2            ),
            .bus3_table_ram_data_convert (bus3_table_ram_data_convert ),
            .bus3_table_wren2            (bus3_table_wren2            ),
            .bus3_table_ram_wr_en_convert(bus3_table_ram_wr_en_convert),
            .bus4_table_addr2            (bus4_table_addr2            ),
            .bus4_table_ram_addr_convert (bus4_table_ram_addr_convert ),
            .bus4_table_data2            (bus4_table_data2            ),
            .bus4_table_ram_data_convert (bus4_table_ram_data_convert ),
            .bus4_table_wren2            (bus4_table_wren2            ),
            .bus4_table_ram_wr_en_convert(bus4_table_ram_wr_en_convert),
            //\u4e0e\u63a5\u6536\u8c03\u5ea6\u63a5\u53e3
            .mac_sour                (mac_sour),
            .port_sour               (port_sour),
            .mac_dest                (mac_dest),
            .mac_addr_en             (uni_addr_en),
            .look_fail               (uni_lookup_fail),
            .busy                    (unicam_busy),
            .outport                 (uni_outport),
            .outport_en              (uni_outport_en),
            //\u4e0eCPU\u914d\u7f6e\u63a5\u53e3
            `ifdef NO_CPU_MODE
            .CPU_write_table_wr_en   (CPU_unicam_wren),
            .CPU_read_table_addr     (CPU_unicam_addr),
            .CPU_write_table_data    (CPU_unicam_din),
            `else
            .CPU_write_table_wr_en   (CPU_unicam_wren),
            .CPU_read_table_addr     (CPU_unicam_addr),
            .CPU_write_table_data    (CPU_unicam_din),
            `endif
            .CPU_read_table_rd_en    (CPU_unicam_rden),
            .CPU_read_table_q        (CPU_unicam_dout),
            .CPU_read_table_q_vld    (CPU_unicam_vld),
            .live_time_val           (CPU_unicam_live_val),
            .live_time_i             (CPU_unicam_live_time),

            .himac_loopback_on_off   (`ifdef NO_CPU_MODE 1'b0  `else himac_loopback_on_off `endif),  //\u56de\u73af\u4e0d\u5f00\u542f\uff0cMAC\u5730\u5740\u5b66\u4e60\u51b2\u7a81
            .broadcast_pkt_pass      (`ifdef NO_CPU_MODE 1'b1  `else broadcast_pkt_pass `endif),  //\u5e7f\u64ad\u5305\u8fc7\u6ee4--1\u8868\u793a\u8fc7\u6ee4
            .broadcast_pkt_ack       (broadcast_pkt_ack),
            .unknow_pkt_pass         (`ifdef NO_CPU_MODE 1'b1 `else unknow_pkt_pass `endif),  //\u672a\u77e5\u5305\u8fc7\u6ee4--1\u8868\u793a\u8fc7\u6ee4
            .unkonw_pkt_ack          (unkonw_pkt_ack),

            .collision_detect_on_off (`ifdef NO_CPU_MODE 1'b1  `else collision_detect_on_off `endif),  //\u51b2\u7a81\u68c0\u6d4b\u5f00\u542f
            .collision_port_1        (collision_port_1),
            .collision_port_2        (collision_port_2),
            .collision_mac_addr_1    (collision_mac_addr_1),
            .collision_mac_addr_2    (collision_mac_addr_2),
            .collision_wren          (collision_wren),
            //\u521d\u59cb\u5316\u5b8c\u6210
            .init_end                (unicam_init_done)
        );
//ME8 \u7ec4\u64ad\u8f6c\u53d1\u8868
  multi_cam_top U_ME8
    (
   .clk                         (clk),
   .rst_n                       (rst_n),
   .ram_dp_cfg_register         (ram_dp_cfg_register),
   //\u4e0eCPU\u914d\u7f6e\u63a5\u53e3
   .wr_en_cpu                   (CPU_mulcam_wren_ff),
   .multi_modify_cpu            (CPU_mulcam_modify),
   .multi_group_mac_cpu         (CPU_mulcam_group_mac),
   .multi_member_cpu            (CPU_mulcam_member),
   .cpu_rd_multicam_rden        (CPU_mulcam_rden),
   .cpu_rd_multicam_address_cpu (CPU_mulcam_addr),
   .cpu_rd_multicam_cpu         (CPU_mulcam_dout),
   .cpu_rd_multicam_cpu_vld     (CPU_mulcam_vld),
   //\u4e0e\u63a5\u6536\u8c03\u5ea6\u63a5\u53e3
   .multi_mac_addr_en           (multi_addr_en),
   .multi_mac_in                (mac_dest[23:0]),
   .multi_group                 (multi_outport),
   .multi_outport_en            (multi_outport_en),
   .multi_busy                  (multi_busy),
   //\u521d\u59cb\u5316\u5b8c\u6210
   .init_end                    (multicam_init_done)
    );
//*********************
//MAIN CORE
//********************* 
always @(*) begin
    casex({me2_action_o[3],me3_4_action_o_ff[3],me5_action_o_ff[3],me6_action_o_ff[3]})
       4'b1xxx : schduler = me2_action_o     ;
       4'b01xx : schduler = me3_4_action_o_ff;
       4'b001x : schduler = me5_action_o_ff  ;
       4'b0001 : schduler = me6_action_o_ff  ;
       default:schduler = 4'b0;
     endcase 
end
//*************************************************************
//\u7531\u4e8e\u65f6\u5e8f\u540c\u6b65\u9700\u6c42\uff0c\u8868\u4e8c\u52a8\u4f5c\u6162\u4e00\u62cd\uff0c\u5c061,3&&4,5,6\u56db\u4e2a\u52a8\u4f5c\u6253\u4e00\u62cd
//*************************************************************
always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        me1_action_o_ff <= 0;
    end else begin
        me1_action_o_ff <= me1_action_o;
    end
end
always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        me3_4_action_o_ff <= 0;
    end else begin
        me3_4_action_o_ff <= me3_4_action_o;
    end
end
always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        me5_action_o_ff <= 0;
    end else begin
        me5_action_o_ff <= me5_action_o;
    end
end
always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        me6_action_o_ff <= 0;
    end else begin
        me6_action_o_ff <= me6_action_o;
    end
end
//*************************************************************
always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
       me1_action_en_o_ff  <= 0;
    end else begin
       me1_action_en_o_ff  <= me1_action_en_o;
    end
end
always @(posedge clk or negedge rst_n) begin
  if(~rst_n) begin
     action_pkt_o      <= 0;
     action_pkt_en_o   <= 0;
  end 
  else if (me1_action_en_o_ff)begin
     action_pkt_o    <= {me1_action_o_ff[84:74],schduler,me1_action_o_ff[73:0]};
     action_pkt_en_o <= 1'b1;
  end
  else begin
     action_pkt_o      <= 0;
     action_pkt_en_o   <= 0;
  end
end
//===============================================================================
wire wr_field;
assign wr_field = np_cpu_ram_ctr[1] && np_cpu_addr[16:10]==`FIELD_SEL_BASE_ADDR;
//ME1
always@(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
       ctr_field0_0      <= 32'b0; 
       ctr_field0_1      <= 32'b0;
       ctr_field0_2      <= 32'b0;
       ctr_field0_3      <= 32'b0;
       ctr_field0_4      <= 32'b0;
       ctr_field0_5      <= 32'b0;
       ctr_field0_6      <= 32'b0;
       ctr_field0_7      <= 32'b0;
    end
    else if(wr_field && np_cpu_addr[5:3]==3'b000) begin
        case(np_cpu_addr[2:0])
            3'h0:ctr_field0_0      <= np_cpu_wr_data;
            3'h1:ctr_field0_1      <= np_cpu_wr_data;
            3'h2:ctr_field0_2      <= np_cpu_wr_data;
            3'h3:ctr_field0_3      <= np_cpu_wr_data;
            3'h4:ctr_field0_4      <= np_cpu_wr_data;
            3'h5:ctr_field0_5      <= np_cpu_wr_data;
            3'h6:ctr_field0_6      <= np_cpu_wr_data;
            3'h7:ctr_field0_7      <= np_cpu_wr_data;
        endcase
        // if(np_cpu_addr[2:0]==0) begin
        //     ctr_field0_0      <= np_cpu_wr_data;
        //     ctr_field0_1      <= ctr_field0_1;
        //     ctr_field0_2      <= ctr_field0_2;
        //     ctr_field0_3      <= ctr_field0_3;
        //     ctr_field0_4      <= ctr_field0_4;
        //     ctr_field0_5      <= ctr_field0_5;
        //     ctr_field0_6      <= ctr_field0_6;
        //     ctr_field0_7      <= ctr_field0_7;
        // end
        // else if(np_cpu_addr[2:0]==1) begin
        //     ctr_field0_0      <= ctr_field0_0;
        //     ctr_field0_1      <= np_cpu_wr_data;
        //     ctr_field0_2      <= ctr_field0_2;
        //     ctr_field0_3      <= ctr_field0_3;
        //     ctr_field0_4      <= ctr_field0_4;
        //     ctr_field0_5      <= ctr_field0_5;
        //     ctr_field0_6      <= ctr_field0_6;
        //     ctr_field0_7      <= ctr_field0_7;
        // end
        // else if (np_cpu_addr[2:0] == 2) begin
        //     ctr_field0_0      <= ctr_field0_0; 
        //     ctr_field0_1      <= ctr_field0_1;
        //     ctr_field0_2      <= np_cpu_wr_data;
        //     ctr_field0_3      <= ctr_field0_3;
        //     ctr_field0_4      <= ctr_field0_4;
        //     ctr_field0_5      <= ctr_field0_5;
        //     ctr_field0_6      <= ctr_field0_6;
        //     ctr_field0_7      <= ctr_field0_7;
        // end
        // else if (np_cpu_addr[2:0] == 3) begin
        //     ctr_field0_0      <= ctr_field0_0; 
        //     ctr_field0_1      <= ctr_field0_1;
        //     ctr_field0_2      <= ctr_field0_2;
        //     ctr_field0_3      <= np_cpu_wr_data;
        //     ctr_field0_4      <= ctr_field0_4;
        //     ctr_field0_5      <= ctr_field0_5;
        //     ctr_field0_6      <= ctr_field0_6;
        //     ctr_field0_7      <= ctr_field0_7;
        // end
        // else if (np_cpu_addr[2:0] == 4) begin
        //     ctr_field0_0      <= ctr_field0_0; 
        //     ctr_field0_1      <= ctr_field0_1;
        //     ctr_field0_2      <= ctr_field0_2;
        //     ctr_field0_3      <= ctr_field0_3;
        //     ctr_field0_4      <= np_cpu_wr_data;
        //     ctr_field0_5      <= ctr_field0_5;
        //     ctr_field0_6      <= ctr_field0_6;
        //     ctr_field0_7      <= ctr_field0_7;
        // end
        // else if (np_cpu_addr[2:0] == 5) begin
        //     ctr_field0_0      <= ctr_field0_0; 
        //     ctr_field0_1      <= ctr_field0_1;
        //     ctr_field0_2      <= ctr_field0_2;
        //     ctr_field0_3      <= ctr_field0_3;
        //     ctr_field0_4      <= ctr_field0_4;
        //     ctr_field0_5      <= np_cpu_wr_data;
        //     ctr_field0_6      <= ctr_field0_6;
        //     ctr_field0_7      <= ctr_field0_7;
        // end
        // else if (np_cpu_addr[2:0] == 6) begin
        //     ctr_field0_0      <= ctr_field0_0; 
        //     ctr_field0_1      <= ctr_field0_1;
        //     ctr_field0_2      <= ctr_field0_2;
        //     ctr_field0_3      <= ctr_field0_3;
        //     ctr_field0_4      <= ctr_field0_4;
        //     ctr_field0_5      <= ctr_field0_5;
        //     ctr_field0_6      <= np_cpu_wr_data;
        //     ctr_field0_7      <= ctr_field0_7;
        // end
        // else if (np_cpu_addr[2:0] == 7) begin
        //     ctr_field0_0      <= ctr_field0_0; 
        //     ctr_field0_1      <= ctr_field0_1;
        //     ctr_field0_2      <= ctr_field0_2;
        //     ctr_field0_3      <= ctr_field0_3;
        //     ctr_field0_4      <= ctr_field0_4;
        //     ctr_field0_5      <= ctr_field0_5;
        //     ctr_field0_6      <= ctr_field0_6;
        //     ctr_field0_7      <= np_cpu_wr_data;
        // end
        // else begin
        //     ctr_field0_0      <= ctr_field0_0; 
        //     ctr_field0_1      <= ctr_field0_1;
        //     ctr_field0_2      <= ctr_field0_2;
        //     ctr_field0_3      <= ctr_field0_3;
        //     ctr_field0_4      <= ctr_field0_4;
        //     ctr_field0_5      <= ctr_field0_5;
        //     ctr_field0_6      <= ctr_field0_6;
        //     ctr_field0_7      <= ctr_field0_7;
        // end
    end
end
assign ctr_field_me1 = {ctr_field0_0,ctr_field0_1,ctr_field0_2,ctr_field0_3,ctr_field0_4,ctr_field0_5,ctr_field0_6,ctr_field0_7};
always@(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
       me_array_filed0_dpram_rdata  <= 32'b0;
            field0_valid                     <= 1'b0;
    end
    else if(rd_field && np_cpu_addr[5:3]==3'b000)begin
        field0_valid                     <= 1'b1;
        case(np_cpu_addr[2:0])
            3'h0:me_array_filed0_dpram_rdata <= ctr_field0_0;
            3'h1:me_array_filed0_dpram_rdata <= ctr_field0_1;
            3'h2:me_array_filed0_dpram_rdata <= ctr_field0_2;
            3'h3:me_array_filed0_dpram_rdata <= ctr_field0_3;
            3'h4:me_array_filed0_dpram_rdata <= ctr_field0_4;
            3'h5:me_array_filed0_dpram_rdata <= ctr_field0_5;
            3'h6:me_array_filed0_dpram_rdata <= ctr_field0_6;
            3'h7:me_array_filed0_dpram_rdata <= ctr_field0_7;
        endcase
    end else begin
        field0_valid                     <= 1'b0;
    end

        // if((np_cpu_addr[2:0] == 0) && rd_field1) begin
        //     me_array_filed1_dpram_rdata      <= ctr_field0_0;
        //     field1_valid                     <= 1'b1;
        // end
        // else if ((np_cpu_addr[2:0] == 1) && rd_field1) begin
        //     me_array_filed1_dpram_rdata      <= ctr_field0_1;
        //     field1_valid                     <= 1'b1;
        // end
        // else if ((np_cpu_addr[2:0] == 2) && rd_field1) begin
        //     me_array_filed1_dpram_rdata      <= ctr_field0_2;
        //     field1_valid                     <= 1'b1;
        // end
        // else if ((np_cpu_addr[2:0] == 3) && rd_field1) begin
        //     me_array_filed1_dpram_rdata      <= ctr_field0_3;
        //     field1_valid                     <= 1'b1;
        // end
        // else if ((np_cpu_addr[2:0] == 4) && rd_field1) begin
        //     me_array_filed1_dpram_rdata      <= ctr_field0_4;
        //     field1_valid                     <= 1'b1;
        // end
        // else if ((np_cpu_addr[2:0] == 5) && rd_field1) begin
        //     me_array_filed1_dpram_rdata      <= ctr_field0_5;
        //     field1_valid                     <= 1'b1;
        // end
        // else if ((np_cpu_addr[2:0] == 6) && rd_field1) begin
        //     me_array_filed1_dpram_rdata      <= ctr_field0_6;
        //     field1_valid                     <= 1'b1;
        // end
        // else if ((np_cpu_addr[2:0] == 7) && rd_field1) begin
        //     me_array_filed1_dpram_rdata      <= ctr_field0_7;
        //     field1_valid                     <= 1'b1;
        // end
        // else begin
        //     me_array_filed1_dpram_rdata  <= 32'b0;
        //     field1_valid                     <= 1'b0;
        // end
    // end
end
//ME2
always@(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
       ctr_field1_0      <= 32'b0; 
       ctr_field1_1      <= 32'b0;
       ctr_field1_2      <= 32'b0;
       ctr_field1_3      <= 32'b0;
    end
    else if(wr_field && np_cpu_addr[5:3]==3'b001) begin
        case(np_cpu_addr[1:0])
            2'h0:ctr_field1_0      <= np_cpu_wr_data;
            2'h1:ctr_field1_1      <= np_cpu_wr_data;
            2'h2:ctr_field1_2      <= np_cpu_wr_data;
            2'h3:ctr_field1_3      <= np_cpu_wr_data;
        endcase
        // if( np_cpu_addr[1:0] == 0 ) begin
        //     ctr_field1_0      <= np_cpu_wr_data;
        //     // ctr_field1_1      <= ctr_field1_1;
        //     // ctr_field1_2      <= ctr_field1_2;
        //     // ctr_field1_3      <= ctr_field1_3;
        // end
        // else if (np_cpu_addr[2:0] == 1) begin
        //     // ctr_field1_0      <= ctr_field1_0;
        //     ctr_field1_1      <= np_cpu_wr_data;
        //     // ctr_field1_2      <= ctr_field1_2;
        //     // ctr_field1_3      <= ctr_field1_3;
        // end
        // else if (np_cpu_addr[2:0] == 2) begin
        //     // ctr_field1_0      <= ctr_field1_0; 
        //     // ctr_field1_1      <= ctr_field1_1;
        //     ctr_field1_2      <= np_cpu_wr_data;
        //     // ctr_field1_3      <= ctr_field1_3;
        // end
        // else if (np_cpu_addr[2:0] == 3) begin
        //     // ctr_field1_0      <= ctr_field1_0; 
        //     // ctr_field1_1      <= ctr_field1_1;
        //     // ctr_field1_2      <= ctr_field1_2;
        //     ctr_field1_3      <= np_cpu_wr_data;
        // end
        // else begin
        //     ctr_field1_0      <= ctr_field1_0; 
        //     ctr_field1_1      <= ctr_field1_1;
        //     ctr_field1_2      <= ctr_field1_2;
        //     ctr_field1_3      <= ctr_field1_3;
        // end
    end
end
assign ctr_field_me2 = {ctr_field1_0,ctr_field1_1,ctr_field1_2,ctr_field1_3};
always@(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
       me_array_filed1_dpram_rdata  <= 32'b0;
            field1_valid                     <= 1'b0;
    end
    else if(rd_field && np_cpu_addr[5:3]==3'b001)begin
        field1_valid                     <= 1'b1;
        case(np_cpu_addr[1:0])
            2'h0:me_array_filed1_dpram_rdata <= ctr_field1_0;
            2'h1:me_array_filed1_dpram_rdata <= ctr_field1_1;
            2'h2:me_array_filed1_dpram_rdata <= ctr_field1_2;
            2'h3:me_array_filed1_dpram_rdata <= ctr_field1_3;
        endcase
        // if((np_cpu_addr[2:0] == 0) && rd_field2) begin
        //     me_array_filed2_dpram_rdata      <= ctr_field1_0;
        //     field2_valid                     <= 1'b1;
        // end
        // else if ((np_cpu_addr[2:0] == 1) && rd_field2) begin
        //     me_array_filed2_dpram_rdata      <= ctr_field1_1;
        //     field2_valid                     <= 1'b1;
        // end
        // else if ((np_cpu_addr[2:0] == 2) && rd_field2) begin
        //     me_array_filed2_dpram_rdata      <= ctr_field1_2;
        //     field2_valid                     <= 1'b1;
        // end
        // else if ((np_cpu_addr[2:0] == 3) && rd_field2) begin
        //     me_array_filed2_dpram_rdata      <= ctr_field1_3;
        //     field2_valid                     <= 1'b1;
        // end
        // else begin
        //     me_array_filed2_dpram_rdata  <= 32'b0;
        //     field2_valid                     <= 1'b0;
        // end
    end else begin
        field1_valid                     <= 1'b0;
    end
end
//ME3
always@(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
       ctr_field2_0      <= 32'b0; 
       ctr_field2_1      <= 32'b0;
       ctr_field2_2      <= 32'b0;
       ctr_field2_3      <= 32'b0;
       ctr_field2_4      <= 32'b0;
       ctr_field2_5      <= 32'b0;
       ctr_field2_6      <= 32'b0;
       ctr_field2_7      <= 32'b0;
    end
    else if(wr_field && np_cpu_addr[5:3]==3'b010) begin
        case(np_cpu_addr[2:0])
            3'h0:ctr_field2_0      <= np_cpu_wr_data;
            3'h1:ctr_field2_1      <= np_cpu_wr_data;
            3'h2:ctr_field2_2      <= np_cpu_wr_data;
            3'h3:ctr_field2_3      <= np_cpu_wr_data;
            3'h4:ctr_field2_4      <= np_cpu_wr_data;
            3'h5:ctr_field2_5      <= np_cpu_wr_data;
            3'h6:ctr_field2_6      <= np_cpu_wr_data;
            3'h7:ctr_field2_7      <= np_cpu_wr_data;
        endcase
        // if( np_cpu_addr[2:0] == 0 ) begin
        //     ctr_field2_0      <= np_cpu_wr_data;
        //     ctr_field2_1      <= ctr_field2_1;
        //     ctr_field2_2      <= ctr_field2_2;
        //     ctr_field2_3      <= ctr_field2_3;
        //     ctr_field2_4      <= ctr_field2_4;
        //     ctr_field2_5      <= ctr_field2_5;
        //     ctr_field2_6      <= ctr_field2_6;
        //     ctr_field2_7      <= ctr_field2_7;
        // end
        // else if (np_cpu_addr[2:0] == 1) begin
        //     ctr_field2_0      <= ctr_field2_0;
        //     ctr_field2_1      <= np_cpu_wr_data;
        //     ctr_field2_2      <= ctr_field2_2;
        //     ctr_field2_3      <= ctr_field2_3;
        //     ctr_field2_4      <= ctr_field2_4;
        //     ctr_field2_5      <= ctr_field2_5;
        //     ctr_field2_6      <= ctr_field2_6;
        //     ctr_field2_7      <= ctr_field2_7;
        // end
        // else if (np_cpu_addr[2:0] == 2) begin
        //     ctr_field2_0      <= ctr_field2_0; 
        //     ctr_field2_1      <= ctr_field2_1;
        //     ctr_field2_2      <= np_cpu_wr_data;
        //     ctr_field2_3      <= ctr_field2_3;
        //     ctr_field2_4      <= ctr_field2_4;
        //     ctr_field2_5      <= ctr_field2_5;
        //     ctr_field2_6      <= ctr_field2_6;
        //     ctr_field2_7      <= ctr_field2_7;
        // end
        // else if (np_cpu_addr[2:0] == 3) begin
        //     ctr_field2_0      <= ctr_field2_0; 
        //     ctr_field2_1      <= ctr_field2_1;
        //     ctr_field2_2      <= ctr_field2_2;
        //     ctr_field2_3      <= np_cpu_wr_data;
        //     ctr_field2_4      <= ctr_field2_4;
        //     ctr_field2_5      <= ctr_field2_5;
        //     ctr_field2_6      <= ctr_field2_6;
        //     ctr_field2_7      <= ctr_field2_7;
        // end
        // else if (np_cpu_addr[2:0] == 4) begin
        //     ctr_field2_0      <= ctr_field2_0; 
        //     ctr_field2_1      <= ctr_field2_1;
        //     ctr_field2_2      <= ctr_field2_2;
        //     ctr_field2_3      <= ctr_field2_3;
        //     ctr_field2_4      <= np_cpu_wr_data;
        //     ctr_field2_5      <= ctr_field2_5;
        //     ctr_field2_6      <= ctr_field2_6;
        //     ctr_field2_7      <= ctr_field2_7;
        // end
        // else if (np_cpu_addr[2:0] == 5) begin
        //     ctr_field2_0      <= ctr_field2_0; 
        //     ctr_field2_1      <= ctr_field2_1;
        //     ctr_field2_2      <= ctr_field2_2;
        //     ctr_field2_3      <= ctr_field2_3;
        //     ctr_field2_4      <= ctr_field2_4;
        //     ctr_field2_5      <= np_cpu_wr_data;
        //     ctr_field2_6      <= ctr_field2_6;
        //     ctr_field2_7      <= ctr_field2_7;
        // end
        // else if (np_cpu_addr[2:0] == 6) begin
        //     ctr_field2_0      <= ctr_field2_0; 
        //     ctr_field2_1      <= ctr_field2_1;
        //     ctr_field2_2      <= ctr_field2_2;
        //     ctr_field2_3      <= ctr_field2_3;
        //     ctr_field2_4      <= ctr_field2_4;
        //     ctr_field2_5      <= ctr_field2_5;
        //     ctr_field2_6      <= np_cpu_wr_data;
        //     ctr_field2_7      <= ctr_field2_7;
        // end
        // else if (np_cpu_addr[2:0] == 7) begin
        //     ctr_field2_0      <= ctr_field2_0; 
        //     ctr_field2_1      <= ctr_field2_1;
        //     ctr_field2_2      <= ctr_field2_2;
        //     ctr_field2_3      <= ctr_field2_3;
        //     ctr_field2_4      <= ctr_field2_4;
        //     ctr_field2_5      <= ctr_field2_5;
        //     ctr_field2_6      <= ctr_field2_6;
        //     ctr_field2_7      <= np_cpu_wr_data;
        // end
        // else begin
        //     ctr_field2_0      <= ctr_field2_0; 
        //     ctr_field2_1      <= ctr_field2_1;
        //     ctr_field2_2      <= ctr_field2_2;
        //     ctr_field2_3      <= ctr_field2_3;
        //     ctr_field2_4      <= ctr_field2_4;
        //     ctr_field2_5      <= ctr_field2_5;
        //     ctr_field2_6      <= ctr_field2_6;
        //     ctr_field2_7      <= ctr_field2_7;
        // end
    end
end
assign ctr_field_me3 = {ctr_field2_0,ctr_field2_1,ctr_field2_2,ctr_field2_3,ctr_field2_4,ctr_field2_5,ctr_field2_6,ctr_field2_7};
always@(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
       me_array_filed2_dpram_rdata  <= 32'b0;
            field2_valid                     <= 1'b0;
    end
    else if(rd_field && np_cpu_addr[5:3]==3'b010)begin
        field2_valid                     <= 1'b1;
        case(np_cpu_addr[2:0])
            3'h0:me_array_filed2_dpram_rdata <= ctr_field2_0;
            3'h1:me_array_filed2_dpram_rdata <= ctr_field2_1;
            3'h2:me_array_filed2_dpram_rdata <= ctr_field2_2;
            3'h3:me_array_filed2_dpram_rdata <= ctr_field2_3;
            3'h4:me_array_filed2_dpram_rdata <= ctr_field2_4;
            3'h5:me_array_filed2_dpram_rdata <= ctr_field2_5;
            3'h6:me_array_filed2_dpram_rdata <= ctr_field2_6;
            3'h7:me_array_filed2_dpram_rdata <= ctr_field2_7;
        endcase
    end else begin
        field2_valid                     <= 1'b0;
    end
    //     if((np_cpu_addr[2:0] == 0) && rd_field3) begin
    //         me_array_filed3_dpram_rdata      <= ctr_field2_0;
    //         field3_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 1) && rd_field3) begin
    //         me_array_filed3_dpram_rdata      <= ctr_field2_1;
    //         field3_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 2) && rd_field3) begin
    //         me_array_filed3_dpram_rdata      <= ctr_field2_2;
    //         field3_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 3) && rd_field3) begin
    //         me_array_filed3_dpram_rdata      <= ctr_field2_3;
    //         field3_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 4) && rd_field3) begin
    //         me_array_filed3_dpram_rdata      <= ctr_field2_4;
    //         field3_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 5) && rd_field3) begin
    //         me_array_filed3_dpram_rdata      <= ctr_field2_5;
    //         field3_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 6) && rd_field3) begin
    //         me_array_filed3_dpram_rdata      <= ctr_field2_6;
    //         field3_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 7) && rd_field3) begin
    //         me_array_filed3_dpram_rdata      <= ctr_field2_7;
    //         field3_valid                     <= 1'b1;
    //     end
    //     else begin
    //         me_array_filed3_dpram_rdata  <= 32'b0;
    //         field3_valid                     <= 1'b0;
    //     end
    // end
end
//ME4
always@(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
       ctr_field3_0      <= 32'b0; 
       ctr_field3_1      <= 32'b0;
       ctr_field3_2      <= 32'b0;
       ctr_field3_3      <= 32'b0;
       ctr_field3_4      <= 32'b0;
       ctr_field3_5      <= 32'b0;
       ctr_field3_6      <= 32'b0;
       ctr_field3_7      <= 32'b0;
    end
    else if(wr_field && np_cpu_addr[5:3]==3'b011) begin
        case(np_cpu_addr[2:0])
            3'h0:ctr_field3_0      <= np_cpu_wr_data;
            3'h1:ctr_field3_1      <= np_cpu_wr_data;
            3'h2:ctr_field3_2      <= np_cpu_wr_data;
            3'h3:ctr_field3_3      <= np_cpu_wr_data;
            3'h4:ctr_field3_4      <= np_cpu_wr_data;
            3'h5:ctr_field3_5      <= np_cpu_wr_data;
            3'h6:ctr_field3_6      <= np_cpu_wr_data;
            3'h7:ctr_field3_7      <= np_cpu_wr_data;
        endcase
        // if( np_cpu_addr[2:0] == 0 ) begin
        //     ctr_field3_0      <= np_cpu_wr_data;
        //     ctr_field3_1      <= ctr_field3_1;
        //     ctr_field3_2      <= ctr_field3_2;
        //     ctr_field3_3      <= ctr_field3_3;
        //     ctr_field3_4      <= ctr_field3_4;
        //     ctr_field3_5      <= ctr_field3_5;
        //     ctr_field3_6      <= ctr_field3_6;
        //     ctr_field3_7      <= ctr_field3_7;
        // end
        // else if (np_cpu_addr[2:0] == 1) begin
        //     ctr_field3_0      <= ctr_field3_0;
        //     ctr_field3_1      <= np_cpu_wr_data;
        //     ctr_field3_2      <= ctr_field3_2;
        //     ctr_field3_3      <= ctr_field3_3;
        //     ctr_field3_4      <= ctr_field3_4;
        //     ctr_field3_5      <= ctr_field3_5;
        //     ctr_field3_6      <= ctr_field3_6;
        //     ctr_field3_7      <= ctr_field3_7;
        // end
        // else if (np_cpu_addr[2:0] == 2) begin
        //     ctr_field3_0      <= ctr_field3_0; 
        //     ctr_field3_1      <= ctr_field3_1;
        //     ctr_field3_2      <= np_cpu_wr_data;
        //     ctr_field3_3      <= ctr_field3_3;
        //     ctr_field3_4      <= ctr_field3_4;
        //     ctr_field3_5      <= ctr_field3_5;
        //     ctr_field3_6      <= ctr_field3_6;
        //     ctr_field3_7      <= ctr_field3_7;
        // end
        // else if (np_cpu_addr[2:0] == 3) begin
        //     ctr_field3_0      <= ctr_field3_0; 
        //     ctr_field3_1      <= ctr_field3_1;
        //     ctr_field3_2      <= ctr_field3_2;
        //     ctr_field3_3      <= np_cpu_wr_data;
        //     ctr_field3_4      <= ctr_field3_4;
        //     ctr_field3_5      <= ctr_field3_5;
        //     ctr_field3_6      <= ctr_field3_6;
        //     ctr_field3_7      <= ctr_field3_7;
        // end
        // else if (np_cpu_addr[2:0] == 4) begin
        //     ctr_field3_0      <= ctr_field3_0; 
        //     ctr_field3_1      <= ctr_field3_1;
        //     ctr_field3_2      <= ctr_field3_2;
        //     ctr_field3_3      <= ctr_field3_3;
        //     ctr_field3_4      <= np_cpu_wr_data;
        //     ctr_field3_5      <= ctr_field3_5;
        //     ctr_field3_6      <= ctr_field3_6;
        //     ctr_field3_7      <= ctr_field3_7;
        // end
        // else if (np_cpu_addr[2:0] == 5) begin
        //     ctr_field3_0      <= ctr_field3_0; 
        //     ctr_field3_1      <= ctr_field3_1;
        //     ctr_field3_2      <= ctr_field3_2;
        //     ctr_field3_3      <= ctr_field3_3;
        //     ctr_field3_4      <= ctr_field3_4;
        //     ctr_field3_5      <= np_cpu_wr_data;
        //     ctr_field3_6      <= ctr_field3_6;
        //     ctr_field3_7      <= ctr_field3_7;
        // end
        // else if (np_cpu_addr[2:0] == 6) begin
        //     ctr_field3_0      <= ctr_field3_0; 
        //     ctr_field3_1      <= ctr_field3_1;
        //     ctr_field3_2      <= ctr_field3_2;
        //     ctr_field3_3      <= ctr_field3_3;
        //     ctr_field3_4      <= ctr_field3_4;
        //     ctr_field3_5      <= ctr_field3_5;
        //     ctr_field3_6      <= np_cpu_wr_data;
        //     ctr_field3_7      <= ctr_field3_7;
        // end
        // else if (np_cpu_addr[2:0] == 7) begin
        //     ctr_field3_0      <= ctr_field3_0; 
        //     ctr_field3_1      <= ctr_field3_1;
        //     ctr_field3_2      <= ctr_field3_2;
        //     ctr_field3_3      <= ctr_field3_3;
        //     ctr_field3_4      <= ctr_field3_4;
        //     ctr_field3_5      <= ctr_field3_5;
        //     ctr_field3_6      <= ctr_field3_6;
        //     ctr_field3_7      <= np_cpu_wr_data;
        // end
        // else begin
        //     ctr_field3_0      <= ctr_field3_0; 
        //     ctr_field3_1      <= ctr_field3_1;
        //     ctr_field3_2      <= ctr_field3_2;
        //     ctr_field3_3      <= ctr_field3_3;
        //     ctr_field3_4      <= ctr_field3_4;
        //     ctr_field3_5      <= ctr_field3_5;
        //     ctr_field3_6      <= ctr_field3_6;
        //     ctr_field3_7      <= ctr_field3_7;
        // end
    end
end
assign ctr_field_me4 = {ctr_field3_0,ctr_field3_1,ctr_field3_2,ctr_field3_3,ctr_field3_4,ctr_field3_5,ctr_field3_6,ctr_field3_7};
always@(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
       me_array_filed3_dpram_rdata  <= 32'b0;
            field3_valid                     <= 1'b0;
    end
    else if(rd_field && np_cpu_addr[5:3]==3'b011)begin
        field3_valid                     <= 1'b1;
        case(np_cpu_addr[2:0])
            3'h0:me_array_filed3_dpram_rdata <= ctr_field3_0;
            3'h1:me_array_filed3_dpram_rdata <= ctr_field3_1;
            3'h2:me_array_filed3_dpram_rdata <= ctr_field3_2;
            3'h3:me_array_filed3_dpram_rdata <= ctr_field3_3;
            3'h4:me_array_filed3_dpram_rdata <= ctr_field3_4;
            3'h5:me_array_filed3_dpram_rdata <= ctr_field3_5;
            3'h6:me_array_filed3_dpram_rdata <= ctr_field3_6;
            3'h7:me_array_filed3_dpram_rdata <= ctr_field3_7;
        endcase
    end else begin
        field3_valid                     <= 1'b0;
    end
    //     if((np_cpu_addr[2:0] == 0) && rd_field4) begin
    //         me_array_filed4_dpram_rdata      <= ctr_field3_0;
    //         field4_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 1) && rd_field4) begin
    //         me_array_filed4_dpram_rdata      <= ctr_field3_1;
    //         field4_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 2) && rd_field4) begin
    //         me_array_filed4_dpram_rdata      <= ctr_field3_2;
    //         field4_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 3) && rd_field4) begin
    //         me_array_filed4_dpram_rdata      <= ctr_field3_3;
    //         field4_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 4) && rd_field4) begin
    //         me_array_filed4_dpram_rdata      <= ctr_field3_4;
    //         field4_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 5) && rd_field4) begin
    //         me_array_filed4_dpram_rdata      <= ctr_field3_5;
    //         field4_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 6) && rd_field4) begin
    //         me_array_filed4_dpram_rdata      <= ctr_field3_6;
    //         field4_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 7) && rd_field4) begin
    //         me_array_filed4_dpram_rdata      <= ctr_field3_7;
    //         field4_valid                     <= 1'b1;
    //     end
    //     else begin
    //         me_array_filed4_dpram_rdata  <= 32'b0;
    //         field4_valid                     <= 1'b0;
    //     end
    // end
end
//ME5
always@(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
       ctr_field4_0      <= 32'b0; 
       ctr_field4_1      <= 32'b0;
       ctr_field4_2      <= 32'b0;
       ctr_field4_3      <= 32'b0;
       ctr_field4_4      <= 32'b0;
       ctr_field4_5      <= 32'b0;
       ctr_field4_6      <= 32'b0;
       ctr_field4_7      <= 32'b0;
    end
    else if(wr_field && np_cpu_addr[5:3]==3'b100) begin
        case(np_cpu_addr[2:0])
            3'h0:ctr_field4_0      <= np_cpu_wr_data;
            3'h1:ctr_field4_1      <= np_cpu_wr_data;
            3'h2:ctr_field4_2      <= np_cpu_wr_data;
            3'h3:ctr_field4_3      <= np_cpu_wr_data;
            3'h4:ctr_field4_4      <= np_cpu_wr_data;
            3'h5:ctr_field4_5      <= np_cpu_wr_data;
            3'h6:ctr_field4_6      <= np_cpu_wr_data;
            3'h7:ctr_field4_7      <= np_cpu_wr_data;
        endcase
        
        // if( np_cpu_addr[2:0] == 0 ) begin
        //     ctr_field4_0      <= np_cpu_wr_data;
        //     ctr_field4_1      <= ctr_field4_1;
        //     ctr_field4_2      <= ctr_field4_2;
        //     ctr_field4_3      <= ctr_field4_3;
        //     ctr_field4_4      <= ctr_field4_4;
        //     ctr_field4_5      <= ctr_field4_5;
        //     ctr_field4_6      <= ctr_field4_6;
        //     ctr_field4_7      <= ctr_field4_7;
        // end
        // else if (np_cpu_addr[2:0] == 1) begin
        //     ctr_field4_0      <= ctr_field4_0;
        //     ctr_field4_1      <= np_cpu_wr_data;
        //     ctr_field4_2      <= ctr_field4_2;
        //     ctr_field4_3      <= ctr_field4_3;
        //     ctr_field4_4      <= ctr_field4_4;
        //     ctr_field4_5      <= ctr_field4_5;
        //     ctr_field4_6      <= ctr_field4_6;
        //     ctr_field4_7      <= ctr_field4_7;
        // end
        // else if (np_cpu_addr[2:0] == 2) begin
        //     ctr_field4_0      <= ctr_field4_0; 
        //     ctr_field4_1      <= ctr_field4_1;
        //     ctr_field4_2      <= np_cpu_wr_data;
        //     ctr_field4_3      <= ctr_field4_3;
        //     ctr_field4_4      <= ctr_field4_4;
        //     ctr_field4_5      <= ctr_field4_5;
        //     ctr_field4_6      <= ctr_field4_6;
        //     ctr_field4_7      <= ctr_field4_7;
        // end
        // else if (np_cpu_addr[2:0] == 3) begin
        //     ctr_field4_0      <= ctr_field4_0; 
        //     ctr_field4_1      <= ctr_field4_1;
        //     ctr_field4_2      <= ctr_field4_2;
        //     ctr_field4_3      <= np_cpu_wr_data;
        //     ctr_field4_4      <= ctr_field4_4;
        //     ctr_field4_5      <= ctr_field4_5;
        //     ctr_field4_6      <= ctr_field4_6;
        //     ctr_field4_7      <= ctr_field4_7;
        // end
        // else if (np_cpu_addr[2:0] == 4) begin
        //     ctr_field4_0      <= ctr_field4_0; 
        //     ctr_field4_1      <= ctr_field4_1;
        //     ctr_field4_2      <= ctr_field4_2;
        //     ctr_field4_3      <= ctr_field4_3;
        //     ctr_field4_4      <= np_cpu_wr_data;
        //     ctr_field4_5      <= ctr_field4_5;
        //     ctr_field4_6      <= ctr_field4_6;
        //     ctr_field4_7      <= ctr_field4_7;
        // end
        // else if (np_cpu_addr[2:0] == 5) begin
        //     ctr_field4_0      <= ctr_field4_0; 
        //     ctr_field4_1      <= ctr_field4_1;
        //     ctr_field4_2      <= ctr_field4_2;
        //     ctr_field4_3      <= ctr_field4_3;
        //     ctr_field4_4      <= ctr_field4_4;
        //     ctr_field4_5      <= np_cpu_wr_data;
        //     ctr_field4_6      <= ctr_field4_6;
        //     ctr_field4_7      <= ctr_field4_7;
        // end
        // else if (np_cpu_addr[2:0] == 6) begin
        //     ctr_field4_0      <= ctr_field4_0; 
        //     ctr_field4_1      <= ctr_field4_1;
        //     ctr_field4_2      <= ctr_field4_2;
        //     ctr_field4_3      <= ctr_field4_3;
        //     ctr_field4_4      <= ctr_field4_4;
        //     ctr_field4_5      <= ctr_field4_5;
        //     ctr_field4_6      <= np_cpu_wr_data;
        //     ctr_field4_7      <= ctr_field4_7;
        // end
        // else if (np_cpu_addr[2:0] == 7) begin
        //     ctr_field4_0      <= ctr_field4_0; 
        //     ctr_field4_1      <= ctr_field4_1;
        //     ctr_field4_2      <= ctr_field4_2;
        //     ctr_field4_3      <= ctr_field4_3;
        //     ctr_field4_4      <= ctr_field4_4;
        //     ctr_field4_5      <= ctr_field4_5;
        //     ctr_field4_6      <= ctr_field4_6;
        //     ctr_field4_7      <= np_cpu_wr_data;
        // end
        // else begin
        //     ctr_field4_0      <= ctr_field4_0; 
        //     ctr_field4_1      <= ctr_field4_1;
        //     ctr_field4_2      <= ctr_field4_2;
        //     ctr_field4_3      <= ctr_field4_3;
        //     ctr_field4_4      <= ctr_field4_4;
        //     ctr_field4_5      <= ctr_field4_5;
        //     ctr_field4_6      <= ctr_field4_6;
        //     ctr_field4_7      <= ctr_field4_7;
        // end
    end
end
assign ctr_field_me5 = {ctr_field4_0,ctr_field4_1,ctr_field4_2,ctr_field4_3,ctr_field4_4,ctr_field4_5,ctr_field4_6,ctr_field4_7};
always@(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
       me_array_filed4_dpram_rdata  <= 32'b0;
            field4_valid                     <= 1'b0;
    end
    else if(rd_field && np_cpu_addr[5:3]==3'b100)begin
        field4_valid                     <= 1'b1;
        case(np_cpu_addr[2:0])
            3'h0:me_array_filed4_dpram_rdata <= ctr_field4_0;
            3'h1:me_array_filed4_dpram_rdata <= ctr_field4_1;
            3'h2:me_array_filed4_dpram_rdata <= ctr_field4_2;
            3'h3:me_array_filed4_dpram_rdata <= ctr_field4_3;
            3'h4:me_array_filed4_dpram_rdata <= ctr_field4_4;
            3'h5:me_array_filed4_dpram_rdata <= ctr_field4_5;
            3'h6:me_array_filed4_dpram_rdata <= ctr_field4_6;
            3'h7:me_array_filed4_dpram_rdata <= ctr_field4_7;
        endcase
    end else begin
        field4_valid                     <= 1'b0;
    end
    // else begin
    //     if((np_cpu_addr[2:0] == 0) && rd_field5) begin
    //         me_array_filed5_dpram_rdata      <= ctr_field4_0;
    //         field5_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 1) && rd_field5) begin
    //         me_array_filed5_dpram_rdata      <= ctr_field4_1;
    //         field5_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 2) && rd_field5) begin
    //         me_array_filed5_dpram_rdata      <= ctr_field4_2;
    //         field5_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 3) && rd_field5) begin
    //         me_array_filed5_dpram_rdata      <= ctr_field4_3;
    //         field5_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 4) && rd_field5) begin
    //         me_array_filed5_dpram_rdata      <= ctr_field4_4;
    //         field5_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 5) && rd_field5) begin
    //         me_array_filed5_dpram_rdata      <= ctr_field4_5;
    //         field5_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 6) && rd_field5) begin
    //         me_array_filed5_dpram_rdata      <= ctr_field4_6;
    //         field5_valid                     <= 1'b1;
    //     end
    //     else if ((np_cpu_addr[2:0] == 7) && rd_field5) begin
    //         me_array_filed5_dpram_rdata      <= ctr_field4_7;
    //         field5_valid                     <= 1'b1;
    //     end
    //     else begin
    //         me_array_filed5_dpram_rdata  <= 32'b0;
    //         field5_valid                 <= 1'b0;
    //     end
    // end
end
  //ME6
  always@(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
       ctr_field5_0      <= 32'b0; 
       ctr_field5_1      <= 32'b0;
       ctr_field5_2      <= 32'b0;
       ctr_field5_3      <= 32'b0;
       ctr_field5_4      <= 32'b0;
       ctr_field5_5      <= 32'b0;
       ctr_field5_6      <= 32'b0;
       ctr_field5_7      <= 32'b0;
    end
    else if(wr_field && np_cpu_addr[5:3]==3'b101) begin
        case(np_cpu_addr[2:0])
            3'h0:ctr_field5_0      <= np_cpu_wr_data;
            3'h1:ctr_field5_1      <= np_cpu_wr_data;
            3'h2:ctr_field5_2      <= np_cpu_wr_data;
            3'h3:ctr_field5_3      <= np_cpu_wr_data;
            3'h4:ctr_field5_4      <= np_cpu_wr_data;
            3'h5:ctr_field5_5      <= np_cpu_wr_data;
            3'h6:ctr_field5_6      <= np_cpu_wr_data;
            3'h7:ctr_field5_7      <= np_cpu_wr_data;
        endcase
    end
  end

  assign ctr_field_me6 = {ctr_field5_0,ctr_field5_1,ctr_field5_2,ctr_field5_3,ctr_field5_4,ctr_field5_5,ctr_field5_6,ctr_field5_7};
  always@(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
       me_array_filed5_dpram_rdata  <= 32'b0;
       field5_valid                 <= 1'b0;
    end
    else if(rd_field && np_cpu_addr[5:3]==3'b101)begin
        field5_valid                     <= 1'b1;
        case(np_cpu_addr[2:0])
            3'h0:me_array_filed5_dpram_rdata <= ctr_field5_0;
            3'h1:me_array_filed5_dpram_rdata <= ctr_field5_1;
            3'h2:me_array_filed5_dpram_rdata <= ctr_field5_2;
            3'h3:me_array_filed5_dpram_rdata <= ctr_field5_3;
            3'h4:me_array_filed5_dpram_rdata <= ctr_field5_4;
            3'h5:me_array_filed5_dpram_rdata <= ctr_field5_5;
            3'h6:me_array_filed5_dpram_rdata <= ctr_field5_6;
            3'h7:me_array_filed5_dpram_rdata <= ctr_field5_7;
        endcase
    end else begin
        field5_valid                     <= 1'b0;
    end
  end

assign rd_field = np_cpu_ram_ctr[0] && np_cpu_addr[16:10]==`FIELD_SEL_BASE_ADDR;
// assign rd_field1 = np_cpu_ram_ctr[0] && np_cpu_addr[16:10]==`FIELD_SEL_BASE_ADDR;
// assign rd_field2 = np_cpu_ram_ctr[0] && np_cpu_addr[16:10]==`FIELD_SEL_BASE_ADDR;
// assign rd_field3 = np_cpu_ram_ctr[0] && np_cpu_addr[16:10]==`FIELD_SEL_BASE_ADDR;
// assign rd_field4 = np_cpu_ram_ctr[0] && np_cpu_addr[16:10]==`FIELD_SEL_BASE_ADDR;
// assign rd_field5 = np_cpu_ram_ctr[0] && np_cpu_addr[16:10]==`FIELD_SEL_BASE_ADDR;
// assign rd_field6 = np_cpu_ram_ctr[0] && np_cpu_addr[16:10]==`FIELD_SEL_BASE_ADDR;
//CPU\u8bfb\u53d6 
//\u7531\u4e8ecase\u592a\u5927\uff0c\u5206\u4e24\u7ea7case\u505a
//first case
assign field_rd_sel  = {field0_valid
                       ,field1_valid
                       ,field2_valid
                       ,field3_valid
                       ,field4_valid
                       ,field5_valid};

assign match_rd_sel  = {me_array_bv1_dpram_valid    
                       ,me_array_rbve1_3_dpram_valid
                       ,me_array_rbve2_3_dpram_valid
                       ,me_array_bv4_dpram_valid    
                       ,me_array_bv5_dpram_valid    
                       ,me_array_bv6_dpram_valid     }; 

assign action_rd_sel = {me_array_action1_dpram_valid
                       ,me_array_action4_dpram_valid
                       ,me_array_action5_dpram_valid
                       ,me_array_action6_dpram_valid};

always @(posedge clk or negedge rst_n) begin
  if (~rst_n)begin
    field_rd_data  <= 32'h0 ;
    field_rd_en <= 1'b0;
  end else begin
    case(1)
      field_rd_sel[5]: begin 
          field_rd_data  <=  me_array_filed0_dpram_rdata; 
          field_rd_en <= 1'b1;
          end 
      field_rd_sel[4]: begin 
          field_rd_data  <=  me_array_filed1_dpram_rdata; 
          field_rd_en <= 1'b1;
          end 
      field_rd_sel[3]: begin 
          field_rd_data  <=  me_array_filed2_dpram_rdata; 
          field_rd_en <= 1'b1;
          end 
      field_rd_sel[2]: begin 
          field_rd_data  <=  me_array_filed3_dpram_rdata; 
          field_rd_en <= 1'b1;
          end 
      field_rd_sel[1]: begin 
          field_rd_data  <=  me_array_filed4_dpram_rdata; 
          field_rd_en <= 1'b1;
          end 
      field_rd_sel[0]: begin 
          field_rd_data  <=  me_array_filed5_dpram_rdata; 
          field_rd_en <= 1'b1;
          end
      default:begin 
        //   field_rd_data  <= field_rd_data ;
          field_rd_en <= 1'b0;
        end
    endcase
  end
end

always @(posedge clk or negedge rst_n) begin
  if (~rst_n)begin
     match_rd_data  <= 32'h0;
     match_rd_en <= 1'b0;
  end else begin
    case(1)
       match_rd_sel[5]:  begin 
           match_rd_data  <=  me_array_bv1_dpram_rdata     ;
           match_rd_en <= 1'b1;
           end
       match_rd_sel[4]:  begin 
           match_rd_data  <=  me_array_rbve1_3_dpram_rdata ;
           match_rd_en <= 1'b1;
           end
       match_rd_sel[3]:  begin 
           match_rd_data  <=  me_array_rbve2_3_dpram_rdata ;
           match_rd_en <= 1'b1;
           end
       match_rd_sel[2]:  begin 
           match_rd_data  <=  me_array_bv4_dpram_rdata     ;
           match_rd_en <= 1'b1;
           end
       match_rd_sel[1]:  begin 
           match_rd_data  <=  me_array_bv5_dpram_rdata     ;
           match_rd_en <= 1'b1;
           end
       match_rd_sel[0]:  begin 
           match_rd_data  <=  me_array_bv6_dpram_rdata     ;
           match_rd_en <= 1'b1;
           end
       default: begin
        //    match_rd_data  <= match_rd_data;
           match_rd_en <= 1'b0;
       end
    endcase
  end
end

always @(posedge clk or negedge rst_n) begin
  if (~rst_n)begin
    action_rd_data  <= 32'h0;
    action_rd_en <= 1'b0;
  end else begin 
    case(1)
       action_rd_sel[3]: begin
            action_rd_data  <=  me_array_action1_dpram_rdata ;
            action_rd_en <= 1'b1;
            end
       action_rd_sel[2]: begin
            action_rd_data  <=  me_array_action4_dpram_rdata ;
            action_rd_en <= 1'b1;
            end
       action_rd_sel[1]: begin
            action_rd_data  <=  me_array_action5_dpram_rdata ;
            action_rd_en <= 1'b1;
            end
       action_rd_sel[0]: begin
            action_rd_data  <=  me_array_action6_dpram_rdata ;
            action_rd_en <= 1'b1;
            end
       default :begin
        //    action_rd_data  <= action_rd_data;
           action_rd_en <= 1'b0;
       end
    endcase
  end
end
///////////////////////////////////////////////////////////////////////
//second case


//assign rd_data_sel = {field_rd_sel,match_rd_sel,action_rd_sel};
assign rd_data_sel = {field_rd_en,match_rd_en,action_rd_en};
always @(posedge clk or negedge rst_n) begin
  if(~rst_n)begin
    np_cpu_rd_data_temp  <= 32'h0;
    class_rd_en_tmp <= 1'b0;
  end else begin
    case(1)
       rd_data_sel[2]: begin
           np_cpu_rd_data_temp  <=  field_rd_data  ;
           class_rd_en_tmp <= 1'b1;
       end 
       rd_data_sel[1]: begin
           np_cpu_rd_data_temp  <=  match_rd_data  ;
           class_rd_en_tmp <= 1'b1;
       end 
       rd_data_sel[0]: begin
           np_cpu_rd_data_temp  <=  action_rd_data ;
           class_rd_en_tmp <= 1'b1;
       end 
       default:begin
        //    np_cpu_rd_data_temp  <= np_cpu_rd_data_temp;
           class_rd_en_tmp <= 1'b0;
       end
    endcase
  end
end

assign class_rd_data = np_cpu_rd_data_temp;
assign class_rd_en = class_rd_en_tmp;




`ifndef NO_CPU_MODE
//=====================================================
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        CPU_reg_wren <= 1'b0;
    else if(np_cpu_ram_ctr[1])
        CPU_reg_wren <= !(|np_cpu_addr[16:10]);
    else
        CPU_reg_wren <= 1'b0;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        CPU_reg_rden <= 1'b0;
    else if(np_cpu_ram_ctr[0])
        CPU_reg_rden <= !(|np_cpu_addr[16:10]);
    else 
        CPU_reg_rden <= 1'b0;
end

// assign CPU_reg_wren = np_cpu_ram_ctr[29];
// assign CPU_reg_rden = np_cpu_ram_ctr[28];
//--------------------------------------------------------
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        CPU_unicam_wren <= 1'b0;
    else if(np_cpu_ram_ctr[1] && np_cpu_addr[16:10]>=`ME7_BASE_ADDR && np_cpu_addr[16:10]<`ME8_BASE_ADDR)
        CPU_unicam_wren <= 1'b1;
    else
        CPU_unicam_wren <= 1'b0;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        CPU_unicam_rden <= 1'b0;
    else if(np_cpu_ram_ctr[0] && np_cpu_addr[16:10]>=`ME7_BASE_ADDR && np_cpu_addr[16:10]<`ME8_BASE_ADDR)
        CPU_unicam_rden <= 1'b1;
    else
        CPU_unicam_rden <= 1'b0;
end
// assign CPU_unicam_wren = np_cpu_ram_ctr[13];
// assign CPU_unicam_rden = np_cpu_ram_ctr[12];
assign CPU_unicam_addr    = np_cpu_addr_d1[11:0];
assign CPU_unicam_din     = np_cpu_wdata_d1;

// assign CPU_mulcam_group_mac = np_cpu_wr_data;
assign CPU_mulcam_addr    = np_cpu_addr_d1[11:0];
assign CPU_mulcam_wren    = CPU_reg_wren && np_cpu_addr_d1[6:0]==`ADDR_DEST_MAC_ADDR ;
assign CPU_mulcam_rden    = np_cpu_ram_ctr[0] && np_cpu_addr[16:10]>=`ME8_BASE_ADDR && np_cpu_addr[16:10]<7'h41;
// always@(posedge clk or negedge rst_n)begin
//     if(~rst_n)begin
//         CPU_unicam_addr_ff <= 'b0;
//         CPU_unicam_din_ff  <= 'b0;
//         CPU_unicam_wren_ff <= 'b0;
//     end
//     else if(CPU_unicam_wren)begin
//         CPU_unicam_addr_ff <= CPU_unicam_addr;
//         CPU_unicam_din_ff  <= CPU_unicam_din;
//         CPU_unicam_wren_ff <= CPU_unicam_wren;
//     end else begin
//         CPU_unicam_addr_ff <= 'b0;
//         CPU_unicam_din_ff  <= 'b0;
//         CPU_unicam_wren_ff <= 'b0;
//     end
// end

always@(posedge clk or negedge rst_n)begin
    if(~rst_n)
        CPU_mulcam_wren_ff       <= 'b0;
    else 
        CPU_mulcam_wren_ff       <= CPU_mulcam_wren;
end


always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        CPU_unicam_live_val <= 1'b0;
    else if(CPU_reg_wren && np_cpu_addr_d1[6:0]==`ADDR_LIVE_TIME_VAL)
        CPU_unicam_live_val <= np_cpu_wdata_d1[0];
    // else 
    //     CPU_unicam_live_val <= CPU_unicam_live_val;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        CPU_unicam_live_time <= 32'b0;
    else if(CPU_reg_wren && np_cpu_addr_d1[6:0]==`ADDR_CAM_LIVE_TIME_STATE)
        CPU_unicam_live_time <= np_cpu_wdata_d1;
    // else 
    //     CPU_unicam_live_time <= CPU_unicam_live_time;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        CPU_mulcam_modify <= 32'b0;
    else if(CPU_reg_wren && np_cpu_addr_d1[6:0]==`ADDR_MULTI_MODIFY)
        CPU_mulcam_modify <= np_cpu_wdata_d1;
    // else 
    //     CPU_mulcam_modify <= CPU_mulcam_modify;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        CPU_mulcam_member <= 32'b0;
    else if(CPU_reg_wren && np_cpu_addr_d1[6:0]==`ADDR_MULTI_CAST)
        CPU_mulcam_member <= np_cpu_wdata_d1;
    // else 
    //     CPU_mulcam_member <= CPU_mulcam_member;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        himac_loopback_on_off <= 1'b0;
    else if(CPU_reg_wren && np_cpu_addr_d1[6:0]==`ADDR_LOOPBACK_ON_OFF)
        himac_loopback_on_off <= np_cpu_wdata_d1[0];
    // else 
    //     himac_loopback_on_off <= himac_loopback_on_off;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        collision_detect_on_off <= 1'b0;
    else if(CPU_reg_wren && np_cpu_addr_d1[6:0]==`ADDR_COLLISION_DETECT_ON_OFF)
        collision_detect_on_off <= np_cpu_wdata_d1[0];
    // else 
    //     collision_detect_on_off <= collision_detect_on_off;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        broadcast_pkt_pass <= 1'b0;
    else if(CPU_reg_wren && np_cpu_addr_d1[6:0]==`ADDR_BROADCAST_PKT_PASS)
        broadcast_pkt_pass <= np_cpu_wdata_d1[0];
    // else 
    //     broadcast_pkt_pass <= broadcast_pkt_pass;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        unknow_pkt_pass <= 1'b0;
    else if(CPU_reg_wren && np_cpu_addr_d1[6:0]==`ADDR_UNKNOW_PKT_PASS)
        unknow_pkt_pass <= np_cpu_wdata_d1[0];
    // else 
    //     unknow_pkt_pass <= unknow_pkt_pass;
end

always @(posedge clk or negedge rst_n) begin//5.23 xym
    if(~rst_n)
        pkt_mod_ctl <= 2'b0;
    else if(CPU_reg_wren && np_cpu_addr_d1[6:0]==`ADDR_ALY_MODE_SEL)
        pkt_mod_ctl <= np_cpu_wdata_d1[1:0];
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        CPU_mulcam_group_mac <= 32'b0;
    else if(CPU_mulcam_wren)
        CPU_mulcam_group_mac <= np_cpu_wdata_d1;
    // else 
    //     CPU_mulcam_group_mac <= CPU_mulcam_group_mac;
end

always@(posedge clk or negedge rst_n)begin
    if(~rst_n)begin
        np_cpu_addr_d1     <= 17'h0;
        CPU_reg_rden_d1    <= 1'h0;
        np_cpu_wdata_d1     <= 32'b0;
    end else begin
        np_cpu_addr_d1     <= np_cpu_addr    ;// 2022.5.9 xym
        // np_cpu_addr_d1     <= {5'b0,np_cpu_addr[10:0]}    ;
        CPU_reg_rden_d1    <= CPU_reg_rden   ;
        np_cpu_wdata_d1     <= np_cpu_wr_data;
    end
end


always @(posedge clk or negedge rst_n) begin
    if(~rst_n)begin
        uni_mul_rd_data <= 32'h0;
        uni_mul_rd_vld <= 1'b0;
    end else if(CPU_unicam_vld)begin
        uni_mul_rd_data <= CPU_unicam_dout;
        uni_mul_rd_vld <= 1'b1;
    end else if(CPU_mulcam_vld) begin
        uni_mul_rd_data <= CPU_mulcam_dout;
        uni_mul_rd_vld <= 1'b1;
    end else begin
        // uni_mul_rd_data <= uni_mul_rd_data;
        uni_mul_rd_vld <= 1'b0;
    end
end

always@(posedge clk or negedge rst_n)begin
    if(~rst_n)begin
        reg_rd_data <= 32'h0;
        CPU_reg_rd_vld <= 1'b0;
    end else if (CPU_reg_rden) begin
        case(np_cpu_addr_d1[6:0])
            `ADDR_COLLISION_SOUR_PORT_1:begin
                reg_rd_data <= {28'b0,collision_port_1};
                CPU_reg_rd_vld <= 1'b1;
                end
            `ADDR_COLLISION_SOUR_PORT_2:begin
                reg_rd_data <= {28'b0,collision_port_2};
                CPU_reg_rd_vld <= 1'b1;
                end
            `ADDR_COLLISION_MAC_ADDR_1_STATE:begin
                reg_rd_data <= collision_mac_addr_1;
                CPU_reg_rd_vld <= 1'b1;
                end
            `ADDR_COLLISION_MAC_ADDR_2_STATE:begin
                reg_rd_data <= {collision_mac_addr_2,16'b1};
                CPU_reg_rd_vld <= 1'b1;
                end
            `ADDR_COLLISION_WREN:begin
                reg_rd_data <= {31'b0,collision_wren};
                CPU_reg_rd_vld <= 1'b1;
                end
            `ADDR_BROADCAST_PKT_ACK:begin
                reg_rd_data <= {31'b0,broadcast_pkt_ack};
                CPU_reg_rd_vld <= 1'b1;
                end
            `ADDR_UNKNOW_PKT_ACK:begin
                reg_rd_data <= {31'b0,unkonw_pkt_ack};
                CPU_reg_rd_vld <= 1'b1;
                end
            `ADDR_CAM_LIVE_TIME_STATE:begin
                reg_rd_data <= CPU_unicam_live_time;
                CPU_reg_rd_vld <= 1'b1;
                end
            `ADDR_LIVE_TIME_VAL:begin
                reg_rd_data <= {31'b0,CPU_unicam_live_val};
                CPU_reg_rd_vld <= 1'b1;
                end
            `ADDR_MULTI_MODIFY:begin
                reg_rd_data <= CPU_mulcam_modify;
                CPU_reg_rd_vld <= 1'b1;
                end
            `ADDR_MULTI_CAST:begin
                reg_rd_data <= CPU_mulcam_member;
                CPU_reg_rd_vld <= 1'b1;
                end
            `ADDR_LOOPBACK_ON_OFF:begin
                reg_rd_data <= {31'b0,himac_loopback_on_off};
                CPU_reg_rd_vld <= 1'b1;
                end
            `ADDR_COLLISION_DETECT_ON_OFF:begin
                reg_rd_data <= {31'b0,collision_detect_on_off};
                CPU_reg_rd_vld <= 1'b1;
                end
            `ADDR_BROADCAST_PKT_PASS:begin
                reg_rd_data <= {31'b0,broadcast_pkt_pass};
                CPU_reg_rd_vld <= 1'b1;
                end
            `ADDR_UNKNOW_PKT_PASS:begin
                reg_rd_data <= {31'b0,unknow_pkt_pass};
                CPU_reg_rd_vld <= 1'b1;
                end
            `ADDR_HASH_ERROR:begin
                reg_rd_data <= {27'b0,me2_hash_error};
                CPU_reg_rd_vld <= 1'b1;
                end
            default:begin
                // reg_rd_data <= reg_rd_data;
                CPU_reg_rd_vld <= 1'b0;
                end
        endcase
    end else begin
        // reg_rd_data <= reg_rd_data;
        CPU_reg_rd_vld <= 1'b0;
    end
end


always@(posedge clk or negedge rst_n)begin
    if(~rst_n)
        np_cpu_rd_data <= 32'b0;
    else if(class_rd_en)
        np_cpu_rd_data <= class_rd_data;
    else if(uni_mul_rd_vld)
        np_cpu_rd_data <= uni_mul_rd_data;
    else if(CPU_reg_rd_vld)
        np_cpu_rd_data <= reg_rd_data;
    // else
    //     np_cpu_rd_data <= np_cpu_rd_data ;
end

always@(posedge clk or negedge rst_n)begin
    if(~rst_n)
        class_8me_rd_vld <= 1'b0;
    else if(class_rd_en||uni_mul_rd_vld||CPU_reg_rd_vld)
        class_8me_rd_vld <= 1'b1; 
    else
        class_8me_rd_vld <= 1'b0;
end
`endif

endmodule    // hookup byte controller block
